The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.01 - January/February (2009 vol.29)
pp: 10-21
Larry Seiler , Intel Corporation
Doug Carmean , Intel Corporation
Eric Sprangle , Intel Corporation
Tom Forsyth , Intel Corporation
Pradeep Dubey , Intel Corporation
Stephen Junkins , Intel Corporation
Adam Lake , Intel Corporation
Robert Cavin , Intel Corporation
Roger Espasa , Intel Corporation
Ed Grochowski , Intel Corporation
Toni Juan , Intel Corporation
Michael Abrash , RAD Game Tools
Jeremy Sugerman , Stanford University
Pat Hanrahan , Stanford University
ABSTRACT
<p>The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The article describes the Larrabee architecture, a software renderer optimized for it, and other highly parallel applications. The article analyzes performance through scalability studies based on real-world workloads. DOI of original article is available at: http://doi.acm.org/10.1145/1399504.1360617</p>
INDEX TERMS
graphics architecture, many-core computing, real-time graphics, software rendering, throughput computing, visual computing, parallel processing, SIMD, GPGPU
CITATION
Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan, "Larrabee: A Many-Core x86 Architecture for Visual Computing", IEEE Micro, vol.29, no. 1, pp. 10-21, January/February 2009, doi:10.1109/MM.2009.9
REFERENCES
1. J. Nickolls, I. Buck, and M. Garland, "Scalable Parallel Programming with CUDA," ACM Queue, vol. 6, no. 2, 2008, pp. 40-53.
2. M. Eldridge, "Designing Graphics Architectures around Scalability and Communication," PhD thesis, Stanford Univ., 2001.
3. L. Seiler et al., "Larrabee: A Many-Core x86 Architecture for Visual Computing," ACM Trans. Graphics, vol. 27, no. 3, 2008, pp. 1-15.
4. N. Greene, "Hierarchical Polygon Tiling with Coverage Masks," Proc. Siggraph, ACM Press, 1996, pp. 65-64.
5. A. Ghuloum et al., "Future-Proof Data Parallel Algorithms and Software on Intel Multi-Core Architectures," Intel Technology J., vol. 11, no. 04, Nov. 2007, pp. 333-348.
6. D. Pham et al., "The Design and Implementation of a First Generation CELL Processor," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2005, pp. 184-186.
51 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool