This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Larrabee: A Many-Core x86 Architecture for Visual Computing
January/February 2009 (vol. 29 no. 1)
pp. 10-21
Larry Seiler, Intel Corporation
Doug Carmean, Intel Corporation
Eric Sprangle, Intel Corporation
Tom Forsyth, Intel Corporation
Pradeep Dubey, Intel Corporation
Stephen Junkins, Intel Corporation
Adam Lake, Intel Corporation
Robert Cavin, Intel Corporation
Roger Espasa, Intel Corporation
Ed Grochowski, Intel Corporation
Toni Juan, Intel Corporation
Michael Abrash, RAD Game Tools
Jeremy Sugerman, Stanford University
Pat Hanrahan, Stanford University

The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic. This increases the architecture's programmability as compared to standard GPUs. The article describes the Larrabee architecture, a software renderer optimized for it, and other highly parallel applications. The article analyzes performance through scalability studies based on real-world workloads. DOI of original article is available at: http://doi.acm.org/10.1145/1399504.1360617

1. J. Nickolls, I. Buck, and M. Garland, "Scalable Parallel Programming with CUDA," ACM Queue, vol. 6, no. 2, 2008, pp. 40-53.
2. M. Eldridge, "Designing Graphics Architectures around Scalability and Communication," PhD thesis, Stanford Univ., 2001.
3. L. Seiler et al., "Larrabee: A Many-Core x86 Architecture for Visual Computing," ACM Trans. Graphics, vol. 27, no. 3, 2008, pp. 1-15.
4. N. Greene, "Hierarchical Polygon Tiling with Coverage Masks," Proc. Siggraph, ACM Press, 1996, pp. 65-64.
5. A. Ghuloum et al., "Future-Proof Data Parallel Algorithms and Software on Intel Multi-Core Architectures," Intel Technology J., vol. 11, no. 04, Nov. 2007, pp. 333-348.
6. D. Pham et al., "The Design and Implementation of a First Generation CELL Processor," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2005, pp. 184-186.
8. G.S. Johnson et al., "The Irregular Z-buffer: Hardware Acceleration for Irregular Data Structures," ACM Trans. Graphics, vol. 24, no. 4, 2005, pp. 1462-1482.
7. A. Bader et al., "Game Physics Performance on the Larrabee Architecture," Intel white paper, 2008; www.intel.com/technology/visualmicroarch.htm .
9. C.J. Hughes et al., "Physical Simulation for Animation and Visual Effects: Parallelization and Characterization for Chip Multiprocessors," Proc. 34th Ann. Int'l Symp. Computer Architecture, ACM Press, 2007, pp. 220-231.
10. Y. Chen et al., "Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications," Proc. IEEE, vol. 96, no. 5, 2008, pp. 790-807.

Index Terms:
graphics architecture, many-core computing, real-time graphics, software rendering, throughput computing, visual computing, parallel processing, SIMD, GPGPU
Citation:
Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan, "Larrabee: A Many-Core x86 Architecture for Visual Computing," IEEE Micro, vol. 29, no. 1, pp. 10-21, Jan.-Feb. 2009, doi:10.1109/MM.2009.9
Usage of this product signifies your acceptance of the Terms of Use.