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Issue No.04 - July/August (2008 vol.28)
pp: 28-40
Dong Hyuk Woo , Georgia Institute of Technology
Marsha Eng , Intel
ABSTRACT
To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.
INDEX TERMS
multicore, multiprocessors, parallel architectures, processor architectures, computer systems organization, physically aware microarchitecture, microarchitecture implementation, processor architectures, power management
CITATION
Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, "POD: A 3D-Integrated Broad-Purpose Acceleration Layer", IEEE Micro, vol.28, no. 4, pp. 28-40, July/August 2008, doi:10.1109/MM.2008.58
REFERENCES
1. S. Borkar, "Thousand Core Chips: A Technology Perspective," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 746-749.
2. W.-M Hwu et al., "Implicitly Parallel Programming Models for Thousand-Core Microprocessors," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 754-759.
3. R. Espasa et al., "Tarantula: A Vector Extension to the Alpha Architecture," Proc. Int'l Symp. Computer Architecture (ISCA 02), IEEE CS Press, 2002, pp. 281-292.
4. W. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 684-689.
5. M.D. Grammatikakis et al., "Packet Routing in Fixed-Connection Networks: A Survey," J. Parallel and Distributed Computing, vol. 54, no. 2, Nov. 1998, pp. 77-132.
6. Y. Cao et al., "New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation," Proc. IEEE Custom Integrated Circuits Conf. (CICC), IEEE Press, 2000, pp. 201-204.
7. R. Gonzalez and M. Horowitz, "Energy Dissipation in General Purpose Microprocessors," IEEE Trans. Solid-State Circuits, vol. 31, no. 9, Sept. 1996, pp. 1277-1284.
8. M.B. Taylor et al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs," IEEE Micro, vol. 22, no. 2, Mar./Apr. 2002, pp. 25-35.
9. J.S. Kim et al., "Energy Characterization of a Tiled Architecture Processor with On-Chip Networks," Proc. 8th Int'l Symp. Low Power Electronics and Design (ISLPED 03), ACM Press, 2003, pp. 424-427.
10. L.-S Peh, "Chip-Scale Networks: Power and Thermal Impact;," www.princeton.edu/∼peh/talksstanford_nws.pdf .
11. H. Wang, L.-S Peh, and S. Malik, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," Proc. Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 105-116.
12. S. Borkar, "Networks for Multi-core Chip: A Controversial View," Proc. 2006 Workshop On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN 06), 2006, www.ece.ucdavis.edu/∼ocin06/talks borkar.pdf.
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