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Fault-Tolerant Design of the IBM Power6 Microprocessor
March/April 2008 (vol. 28 no. 2)
pp. 30-38
Kevin Reick, IBM Systems & Technology Group
Pia N. Sanda, IBM Systems & Technology Group
Scott Swaney, IBM Systems & Technology Group
Jeffrey W. Kellington, IBM Systems & Technology Group
Michael Mack, IBM Systems & Technology Group
Michael Floyd, IBM Systems & Technology Group
Daniel Henderson, IBM Systems & Technology Group
The IBM Power6 microprocessor extends the capabilities of the Power5, dramatically increasing its ability to recover from hard and soft errors without increasing system downtime. The Power6 adds new mainframe-like features for enhanced reliability, availability, and serviceability, including instruction retry and processor failover. Optimized for performance and power, the Power6 implements these RAS enhancements without compromising ultrahigh-frequency operation.

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Index Terms:
Hot Chips 19, RAS, fault tolerance, fault isolation, reliability, instruction retry
Citation:
Kevin Reick, Pia N. Sanda, Scott Swaney, Jeffrey W. Kellington, Michael Mack, Michael Floyd, Daniel Henderson, "Fault-Tolerant Design of the IBM Power6 Microprocessor," IEEE Micro, vol. 28, no. 2, pp. 30-38, March-April 2008, doi:10.1109/MM.2008.22
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