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Issue No.02 - March/April (2008 vol.28)
pp: 19-29
ABSTRACT
The IBM System z10 includes four microprocessor cores—each with a private 3-Mbyte cache—and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.
INDEX TERMS
Hot Chips 19, microprocessor, pipeline, accelerators, mainframe, symmetric multiprocessor (SMP), branch prediction, high-frequency design, reliability, decimal floating-point
CITATION
Charles F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor", IEEE Micro, vol.28, no. 2, pp. 19-29, March/April 2008, doi:10.1109/MM.2008.26
REFERENCES
1. z/Architecture Principles of Operation, document no. SA22-7832, IBM, 2000.
2. J. Friedrich et al., "Design of the Power6 Microprocessor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 96-97.
3. L. Eisen et al., "IBM Power6 Accelerators: VMX and DFU," IBM J. Research and Development, vol. 51, no. 6, Nov. 2007, pp. 663-684.
4. A. Duale et al., "Decimal Floating-Point in z9: An Implementation and Testing Perspective," IBM J. Research and Development, vol. 51, no. 1 and 2, Jan.-Mar. 2007, pp. 217-228.
5. C.F. Webb and J.S. Liptay, "A High-Frequency Custom CMOS S/390 Microprocessor," IBM J. Research and Development, vol. 41, no. 4 and 5, 1997, pp. 463-474.
6. T.J. Slegel et al., "IBM's S/390 G5 Microprocessor," IEEE Micro, vol. 19, no. 2, Mar.-Apr. 1999, pp. 12-23.
7. E.M. Schwarz et al., "The Microarchitecture of the IBM eServer z900 Processor," IBM J. Research and Development, vol. 46, no. 4 and 5, 2002, pp. 381-396.
8. T.J. Slegel, E. Pfeffer, and J.A. Magee, "The IBM eServer z990 Microprocessor," IBM J. Research and Development, vol. 48, no. 3 and 4, 2004, pp. 295-310.
9. A. Hartstein and T.R. Puzak, "The Optimum Pipeline Depth for a Microprocessor," Proc. 29th Ann. Symp. Computer Architecture (ISCA 02), IEEE CS Press, 2002, pp. 7-13.
10. M.S. Hrishikesh, N.P. Jouppi, and K.I. Farkas, "The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays," Proc. 29th Ann. Symp. Computer Architecture (ISCA 02), IEEE CS Press, 2002, pp. 14-24.
11. C.F. Webb, "S/390 Microprocessor Design," IBM J. Research and Development, vol. 44, no. 6, 2000, pp. 899-908.
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