Issue No.02 - March/April (2008 vol.28)
Charles F. Webb , IBM
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2008.26
The IBM System z10 includes four microprocessor cores—each with a private 3-Mbyte cache—and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.
Hot Chips 19, microprocessor, pipeline, accelerators, mainframe, symmetric multiprocessor (SMP), branch prediction, high-frequency design, reliability, decimal floating-point
Charles F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor", IEEE Micro, vol.28, no. 2, pp. 19-29, March/April 2008, doi:10.1109/MM.2008.26