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| Michael R. Marty, Mark D. Hill, "Virtual Hierarchies," IEEE Micro, vol. 28, no. 1, pp. 99-109, January/February, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2008.19, author = {Michael R. Marty and Mark D. Hill}, title = {Virtual Hierarchies}, journal ={IEEE Micro}, volume = {28}, number = {1}, issn = {0272-1732}, year = {2008}, pages = {99-109}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.19}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Virtual Hierarchies IS - 1 SN - 0272-1732 SP99 EP109 EPD - 99-109 A1 - Michael R. Marty, A1 - Mark D. Hill, PY - 2008 KW - virtual hierarchies KW - space sharing KW - server consolidation KW - virtual machines KW - partitioning KW - multicore KW - chip multiprocessors (CMPs) KW - cache coherence VL - 28 JA - IEEE Micro ER - | |||
1. C.A. Waldspurger, "Memory Resource Management in VMware ESX Server," Proc. 5th Symp. Operating Systems Design and Implementation (OSDI 02), ACM Press, 2002, pp. 181-194.
2. E. Hagersten and M. Koster, "WildFire: A Scalable Path for SMPs," Proc. 5th IEEE Symp. High-Performance Computer Architecture (HPCA 99), IEEE CS Press, 1999, pp. 172-181.
3. M.M.K. Martin, M.D. Hill, and D.A. Wood, "Token Coherence: Decoupling Performance and Correctness," Proc. 30th Ann. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 182-193.
4. A. Gupta and W.-D Weber, "Cache Invalidation Patterns in Shared-Memory Multiprocessors," IEEE Trans. Computers, vol. 41, no, 7, Jul. 1992, pp. 794-810.
5. M.R. Marty and M.D. Hill, "Coherence Ordering for Ring-Based Chip Multiprocessors," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 309-320.
6. M.R. Marty et al., "Improving Multiple-CMP Systems Using Token Coherence," Proc. 11th IEEE Symp. High-Performance Computer Architecture (HPCA 05), IEEE CS Press, 2005, pp. 328-339.
7. M.R. Marty et al., "Virtual Hierarchies to Support Server Consolidation," Proc. 34th Ann. Int'l Symp. Computer Architecture (ISCA 07), IEEE CS Press, 2007, pp. 46-56.
8. M.M. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News,, Sept. 2005, pp. 92-99.
9. K.J. Nesbit et al., "Fair Queuing CMP Memory Systems," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 208-222.
10. A.R. Alameldeen and D.A. Wood, "IPC Considered Harmful for Multiprocessor Workloads," IEEE Micro, vol. 26, no. 4, Jul./Aug. 2006, pp. 8-17.
11. A.R. Alameldeen and D.A. Wood, "Variability in Architectural Simulations of Multi-threaded Workloads," Proc. 9th IEEE Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 7-18.
12. C. Kim, D. Burger, and S.W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 211-222.
13. M. Zhang and K. Asanovic, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 336-345.
14. L.A. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 282-293.
15. J. Chang and G.S. Sohi, "Cooperative Caching for Chip Multiprocessors," Proc. 33rd Ann. Int'l Symp. Computer Architecture (ISCA 06), IEEE CS Press, 2006, pp. 264-276.
16. J. Huh et al., "A NUCA Substrate for Flexible CMP Cache Sharing," Proc. 19th Int'l Conf. Supercomputing (ICS 05), ACM Press, 2005, pp. 31-40.

