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Toward Ideal On-Chip Communication Using Express Virtual Channels
January/February 2008 (vol. 28 no. 1)
pp. 80-90
Amit Kumar, Princeton University
Li-Shiuan Peh, Princeton University
Partha Kundu, Microprocessor Technology Labs, Intel
Niraj K. Jha, Princeton University
Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

1. K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," Proc. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 422-433.
2. M.B. Taylor et al., "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams," Proc. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 2-13.
3. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
4. W.J. Dally and B. Towles, "Route Packets Not Wires: On-Chip Interconnection Networks," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 684-689.
5. J.A. Kahle et al., "Introduction to the Cell Multiprocessor," IBM J. Research and Development, vol. 49, no. 4 and 5, 2005, pp. 589-604.
6. M. Galles, "Scalable Pipelined Interconnect for Distributed Endpoint Routing: The SGI SPIDER Chip," Hot Interconnects 4,, 1996, pp. 141-146.
7. L.-S Peh and W.J. Dally, "A Delay Model and Speculative Architecture for Pipelined Routers," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA 01), IEEE CS Press, 2001, pp. 255-266.
8. W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
9. H.-S Wang et al., "Orion: A Power-Performance Simulator for Interconnection Networks," Proc. Int'l Symp. Microarchitecture (MICRO 02), IEEE CS Press, 2002, pp. 294-305.
10. W.J. Dally, "Virtual-Channel Flow Control," Proc. Int'l Symp. Computer Architecture (ISCA 90), ACM Press, 1990, pp. 60-68.

Index Terms:
flow control, packet switching, router design, on-chip interconnects
Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha, "Toward Ideal On-Chip Communication Using Express Virtual Channels," IEEE Micro, vol. 28, no. 1, pp. 80-90, Jan.-Feb. 2008, doi:10.1109/MM.2008.18
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