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Architecting Efficient Interconnects for Large Caches with CACTI 6.0
January/February 2008 (vol. 28 no. 1)
pp. 69-79
Naveen Muralimanohar, University of Utah
Rajeev Balasubramonian, University of Utah
Norman P. Jouppi, Hewlett-Packard Laboratories
Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. An enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. The new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

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Index Terms:
on-chip interconnects, CACTI 6.0, cache design
Citation:
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi, "Architecting Efficient Interconnects for Large Caches with CACTI 6.0," IEEE Micro, vol. 28, no. 1, pp. 69-79, Jan.-Feb. 2008, doi:10.1109/MM.2008.2
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