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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability
January/February 2008 (vol. 28 no. 1)
pp. 60-68
Xiaoyao Liang, Harvard University
Ramon Canal, Universitat Politècnica de Catalunya
Gu-Yeon Wei, Harvard University
David Brooks, Harvard University
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.

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Index Terms:
variability, process variation, caches, dynamic memory
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability," IEEE Micro, vol. 28, no. 1, pp. 60-68, Jan.-Feb. 2008, doi:10.1109/MM.2008.12
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