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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
January/February 2008 (vol. 28 no. 1)
pp. 52-59
ASCII Text
x 
 
Albert Meixner, Michael E. Bauer, Daniel J. Sorin, "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores," IEEE Micro, vol. 28, no. 1, pp. 52-59, January/February, 2008.
 
 
BibTex
x
 
@article{ 10.1109/MM.2008.3,
author = {Albert Meixner and Michael E. Bauer and Daniel J. Sorin},
title = {Argus: Low-Cost, Comprehensive Error Detection in Simple Cores},
journal ={IEEE Micro},
volume = {28},
number = {1},
issn = {0272-1732},
year = {2008},
pages = {52-59},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.3},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
IS - 1
SN - 0272-1732
SP52
EP59
EPD - 52-59
A1 - Albert Meixner,
A1 - Michael E. Bauer,
A1 - Daniel J. Sorin,
PY - 2008
KW - microarchitecture
KW - error detection
KW - dependability
KW - fault tolerance
VL - 28
JA - IEEE Micro
ER -
 
Albert Meixner, Duke University
Michael E. Bauer, Duke University
Daniel J. Sorin, Duke University
Argus, a novel approach for detecting errors in simple processor cores, dynamically verifies the correctness of the four tasks performed by a von Neumann core: control flow, data flow, computation, and memory access. Argus detects transient and permanent errors, with far lower impact on performance and chip area than previous techniques.

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Index Terms:
microarchitecture, error detection, dependability, fault tolerance
Citation:
Albert Meixner, Michael E. Bauer, Daniel J. Sorin, "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores," IEEE Micro, vol. 28, no. 1, pp. 52-59, Jan.-Feb. 2008, doi:10.1109/MM.2008.3
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