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Performance Pathologies in Hardware Transactional Memory
January/February 2008 (vol. 28 no. 1)
pp. 32-41
Jayaram Bobba, University of Wisconsin—Madison
Kevin E. Moore, Sun Microsystems
Haris Volos, University of Wisconsin—Madison
Luke Yen, University of Wisconsin—Madison
Mark D. Hill, University of Wisconsin—Madison
Michael M. Swift, University of Wisconsin—Madison
David A. Wood, University of Wisconsin—Madison
Transactional memory is a promising approach to ease parallel programming. Hardware transactional memory system designs reflect choices along three key design dimensions: conflict detection, version management, and conflict resolution. The authors identify a set of performance pathologies that could degrade performance in proposed HTM designs. Improving conflict resolution could eliminate these pathologies so designers can build robust HTM systems.

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Index Terms:
transactional memory, pathology, hardware transactional memory, conflict resolution, version management, conflict detection
Citation:
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood, "Performance Pathologies in Hardware Transactional Memory," IEEE Micro, vol. 28, no. 1, pp. 32-41, Jan.-Feb. 2008, doi:10.1109/MM.2008.11
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