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Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation
January/February 2008 (vol. 28 no. 1)
pp. 21-31
ASCII Text
x 
 
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig Zilles, "Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation," IEEE Micro, vol. 28, no. 1, pp. 21-31, January/February, 2008.
 
 
BibTex
x
 
@article{ 10.1109/MM.2008.7,
author = {Naveen Neelakantam and Ravi Rajwar and Suresh Srinivas and Uma Srinivasan and Craig Zilles},
title = {Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation},
journal ={IEEE Micro},
volume = {28},
number = {1},
issn = {0272-1732},
year = {2008},
pages = {21-31},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation
IS - 1
SN - 0272-1732
SP21
EP31
EPD - 21-31
A1 - Naveen Neelakantam,
A1 - Ravi Rajwar,
A1 - Suresh Srinivas,
A1 - Uma Srinivasan,
A1 - Craig Zilles,
PY - 2008
KW - compiler-architecture interactions
KW - architecture
KW - atomicity
KW - checkpoint
KW - compiler
KW - isolation
KW - Java
KW - optimization
KW - speculation
VL - 28
JA - IEEE Micro
ER -
 
Naveen Neelakantam, University of Illinois at Urbana-Champaign
Ravi Rajwar, Intel
Craig Zilles, University of Illinois at Urbana-Champaign
Hardware support for atomic execution can both greatly simplify the implementation of existing speculative compiler optimizations and enable new ones. Given current technology trends, this hardware and software cooperation is a compelling approach; such optimizations can simultaneously improve single-thread performance and reduce power consumption in both sequential and multithreaded applications.

1. S.M. Blackburn et al., "The DaCapo Benchmarks: Java Benchmarking Development and Analysis," Proc. 21st Ann. ACM SIGPLAN Conf. Object-Oriented Programming Systems, Languages, and Applications (OOPSLA 06), ACM Press, 2006, pp. 169-190.
2. R. Muth and S. Debray, "Partial Inlining," tech. report, Dept. of Computer Science, Univ. of Arizona, 1997.
3. H. Akkary, R. Rajwar, and S.T. Srinivasan, "Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 423-434.
4. N. Neelakantam et al., "Hardware Atomicity for Reliable Software Speculation," Proc. 34th Ann. Int'l Symp. Computer Architecture (ISCA 07), IEEE CS Press, 2007, pp. 174-185.
5. K. Kawachiya, A. Koseki, and T. Onodera, "Lock Reservation: Java Locks Can Mostly Do Without Atomic Operations," Proc. 17th Ann. ACM SIGPLAN Conf. Object-Oriented Programming Systems, Languages, and Applications (OOPSLA 02), ACM Press, 2002, pp. 130-141.
6. J. Manson, W. Pugh, and S.V. Adve, "The Java Memory Model," Proc. 32nd ACM SIGPLAN-SIGACT Symp. Principles of Programming Languages (POPL 05), ACM Press, 2005, pp. 378-391.
7. R. Rajwar and J.R. Goodman, "Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution," Proc. 34th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 01), IEEE CS Press, 2001, pp. 294-305.
8. C. Zilles and N. Neelakantam, "Reactive Techniques for Controlling Software Speculation," Proc. Int'l Symp. Code Generation and Optimization (CGO 05), ACM Press, 2005, pp. 305-316.
9. J.R. Larus and R. Rajwar, Transactional Memory, Morgan and Claypool, 2006.
10. S. Melvin and Y. Patt, "Enhancing Instruction Scheduling with a Block-Structured ISA," Int'l J. Parallel Programming, vol. 23, no. 3, 1995, pp. 221-243.
11. S.J. Patel and S.S. Lumetta, "rePLay: A Hardware Framework for Dynamic Optimization," IEEE Trans. Computers, vol. 50, no. 6, 2001, pp. 590-608.
12. J.C. Dehnert et al., "The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges," Proc. Int'l Symp. Code Generation and Optimization (CGO), ACM Press, 2003, pp. 15-24.
13. W.A. Wulf, "Compilers and Computer Architecture," Computer, vol. 14, no. 7, 1981, pp. 41-47.
1. G. Hamerly et al., "SimPoint 3.0: Faster and More Flexible Program Analysis,"J. Instruction Level Parallelism, vol. 7, Sept. 2005, pp. 1-28, www.jilp.org/vol7v7paper14.pdf
2. E. Perelman et al., "Cross Binary Simulation Points,"Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS), IEEE CS Press, 2007, pp. 179-189.

Index Terms:
compiler-architecture interactions, architecture, atomicity, checkpoint, compiler, isolation, Java, optimization, speculation
Citation:
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig Zilles, "Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation," IEEE Micro, vol. 28, no. 1, pp. 21-31, Jan.-Feb. 2008, doi:10.1109/MM.2008.7
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