CSDL - IEEE Micro

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Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007 (HTML)

Features

Sarita Adve, University of Illinois, Urbana-Champaign

David Brooks, Harvard

Craig Zilles, University of Illinois, Urbana-Champaign

pp. 8-11

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Revisiting the Sequential Programming Model for the Multicore Era (Abstract)

Matthew J. Bridges, Princeton University

Neil Vachharajani, Princeton University

Yun Zhang, Princeton University

Thomas Jablin, Princeton University

David I. August, Princeton University

pp. 12-20

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Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation (Abstract)

Naveen Neelakantam, University of Illinois at Urbana-Champaign

Ravi Rajwar, Intel

Suresh Srinivas, Intel

Uma Srinivasan, Intel

Craig Zilles, University of Illinois at Urbana-Champaign

pp. 21-31

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Performance Pathologies in Hardware Transactional Memory (Abstract)

Jayaram Bobba, University of Wisconsin—Madison

Kevin E. Moore, Sun Microsystems

Haris Volos, University of Wisconsin—Madison

Luke Yen, University of Wisconsin—Madison

Mark D. Hill, University of Wisconsin—Madison

Michael M. Swift, University of Wisconsin—Madison

David A. Wood, University of Wisconsin—Madison

pp. 32-41

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MetaTM/TxLinux: Transactional Memory for an Operating System (Abstract)

Hany E. Ramadan, University of Texas at Austin

Christopher J. Rossbach, University of Texas at Austin

Donald E. Porter, University of Texas at Austin

Owen S. Hofmann, University of Texas at Austin

Aditya Bhandari, University of Texas at Austin

Emmett Witchel, University of Texas at Austin

pp. 42-51

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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores (Abstract)

Albert Meixner, Duke University

Michael E. Bauer, Duke University

Daniel J. Sorin, Duke University

pp. 52-59

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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability (Abstract)

Xiaoyao Liang, Harvard University

Ramon Canal, Universitat Politècnica de Catalunya

Gu-Yeon Wei, Harvard University

David Brooks, Harvard University

pp. 60-68

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Architecting Efficient Interconnects for Large Caches with CACTI 6.0 (Abstract)

Naveen Muralimanohar, University of Utah

Rajeev Balasubramonian, University of Utah

Norman P. Jouppi, Hewlett-Packard Laboratories

pp. 69-79

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Toward Ideal On-Chip Communication Using Express Virtual Channels (Abstract)

Amit Kumar, Princeton University

Li-Shiuan Peh, Princeton University

Partha Kundu, Microprocessor Technology Labs, Intel

Niraj K. Jha, Princeton University

pp. 80-90

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Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching (Abstract)

Moinuddin K. Qureshi, IBM Research

Aamer Jaleel, Intel

Yale N. Patt, The University of Texas at Austin

Simon C. Steely Jr., Intel

Joel Emer, Intel

pp. 91-98

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Virtual Hierarchies (Abstract)

Michael R. Marty, University of Wisconsin—Madison

Mark D. Hill, University of Wisconsin—Madison

pp. 99-109

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Micro Innovations

A Collaborative IP-Development Session (Abstract)

Philip Emma, IBM T.J. Watson Research Center

pp. 112, 110-111

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