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Issue No.05 - September/October (2007 vol.27)
pp: 96-108
John D. Owens , University of California, Davis
William J. Dally , Stanford University
Ron Ho , Sun Microsystems
D.N. (Jay) Jayasimha , Intel Corporation
Stephen W. Keckler , University of Texas at Austin
Li-Shiuan Peh , Princeton University
ABSTRACT
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems. Last year, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.
INDEX TERMS
on-chip interconnection networks, network on chip, system on chip, embedded systems, multicore architectures
CITATION
John D. Owens, William J. Dally, Ron Ho, D.N. (Jay) Jayasimha, Stephen W. Keckler, Li-Shiuan Peh, "Research Challenges for On-Chip Interconnection Networks", IEEE Micro, vol.27, no. 5, pp. 96-108, September/October 2007, doi:10.1109/MM.2007.91
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