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Research Challenges for On-Chip Interconnection Networks
September/October 2007 (vol. 27 no. 5)
pp. 96-108
John D. Owens, University of California, Davis
William J. Dally, Stanford University
Ron Ho, Sun Microsystems
D.N. (Jay) Jayasimha, Intel Corporation
Stephen W. Keckler, University of Texas at Austin
Li-Shiuan Peh, Princeton University
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems. Last year, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.

1. "Special Session: Thousand-Core Chips," 44th Design Automation Conf., 2007, http://www2.dac.com/data2/44th/44acceptedpapers.nsf/ websessions42.
2. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Conf. Design Automation (DAC 01), ACM Press, 2001, pp. 684-689.
3. R. Ho, K. Mai, and M. Horowitz, "Managing Wire Scaling: A Circuit Perspective," Proc. IEEE Int'l Interconnect Technology Conf., IEEE Press, 2003, pp. 177-179.
4. K. Bergman et al., "Optical On-Chip Networks for High-Performance, Energy-Efficient Multi-Core Architectures," poster session, Workshop On- and Off-Chip Interconnection Networks for Multicore Systems, Dec. 2006, http://www.ece.ucdavis.edu/∼ocin06 posters.html.
5. Intel's Teraflops Research Chip, 2007, http://techresearch.intel.com/articles/Tera-Scale 1449.htm.
6. P. Gratz et al., "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), 2007, pp. 7-17.
7. "STMicroelectronics Unveils Innovative Network-on-Chip Technology for New System-on-Chip Interconnect Paradigm," press release, Dec. 2005, http://www.st.com/stonline/press/news/year2005 t1741t.htm.
8. "Sonics Defines SoC Interconnect Choices," press release, June 2006, http://findarticles.com/p/articles/mi_m0EIN/ is_2006_June_26ai_n16499393.
9. E.A. Brewer et al., "Remote Queues: Exposing Message Queues for Optimization and Atomicity," Proc. 7th Ann. ACM Symp. Parallel Algorithms and Architectures (SPAA 95), ACM Press, 1995, pp. 42-53.
10. W.J. Dally et al., "The Message-Driven Processor: A Multicomputer Processing Node with Efficient Mechanisms," IEEE Micro, vol. 12, no. 2, Mar.-Apr. 1992, pp. 23-39.
11. R. Mullins, A. West, and S. Moore, "Low-Latency Virtual-Channel Routers for On-Chip Networks," Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 188-197.
12. N. Eisley, L.-S Peh, and L. Shang, "In-Network Cache Coherence," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 321-332.
13. J. Held, J. Bautista, and S. Koehl, "From a Few Cores to Many: A Tera-Scale Computing Research Overview," 2006, http://download.intel.com/research/platform/ terascaleterascale_overview_paper.pdf .
14. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
15. M. Katevenis, "Towards Light-Weight Intra-CMP Network Interfaces," Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems, Dec. 2006. http://www.ece.ucdavis.edu/˜ocin06 program.html.
16. J. Duato et al., "Part I: A Theory for Deadlock-Free Dynamic Reconfiguration of Interconnection Networks," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 5, May 2005, pp. 412-427.
17. J.L. Henning, "SPEC CPU2006 Benchmark Descriptions," SIGARCH Computer Architecture News, vol. 34, no. 4, Sept. 2006, pp. 1-17.
18. C. Grecu et al., "An Initiative towards Open Network-on-Chip Benchmarks," 2007, http://www.ocpip.org/socket/whitepapersNoC-Benchmarks-WhitePaper-15.pdf .
19. J. Rattner, "Cool Codes for Hot Chips," Hot Chips 18, 2006, http://www.hotchips.org/archives/hc18/2_Mon/ HC18.Keynote%20OneHC18.Keynote1.pdf .

Index Terms:
on-chip interconnection networks, network on chip, system on chip, embedded systems, multicore architectures
Citation:
John D. Owens, William J. Dally, Ron Ho, D.N. (Jay) Jayasimha, Stephen W. Keckler, Li-Shiuan Peh, "Research Challenges for On-Chip Interconnection Networks," IEEE Micro, vol. 27, no. 5, pp. 96-108, Sept.-Oct. 2007, doi:10.1109/MM.2007.91
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