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Issue No.05 - September/October (2007 vol.27)
pp: 75-85
Federico Angiolini , Università di Bologna
Srinivasan Murali , École Polytechnique Fédérale de Lausanne
David Atienza , Universidad Complutense de Madrid
Antonio Pullini , Politecnico di Torino
Luca Benini , Università di Bologna
ABSTRACT
Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.
INDEX TERMS
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
CITATION
Federico Angiolini, Srinivasan Murali, David Atienza, Antonio Pullini, Luca Benini, "Bringing NoCs to 65 nm", IEEE Micro, vol.27, no. 5, pp. 75-85, September/October 2007, doi:10.1109/MM.2007.79
REFERENCES
1. L. Benini and G. De Micheli, "Networks on Chip: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
2. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Conf. Design Automation (DAC 01), ACM Press, 2001, pp. 684-689.
3. F. Angiolini et al., "Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness," Proc. Design, Automation and Test in Europe Conf. (DATE 06), IEEE Press, 2006, pp. 124-129.
4. A. Jantsch and H. Tenhunen eds. Networks on Chip, Kluwer Academic, 2003.
5. L. Benini, and G.D. Micheli eds. , Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006.
6. A. Pullini et al., "Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes," Proc. 18th Ann. Symp. Integrated Circuits and System Design (SBCCI 05), ACM Press, 2005, pp. 224-229.
7. S. Murali et al., "Designing Application-Specific Networks on Chips with Floorplan Information," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE Press, 2006, pp. 355-362.
8. A. Pullini et al., "NoC Design and Implementation in 65 nm Technology," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE Press, 2007, pp. 273-282.
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