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Issue No.05 - September/October (2007 vol.27)
pp: 75-85
Antonio Pullini , Politecnico di Torino
Federico Angiolini , Università di Bologna
Srinivasan Murali , École Polytechnique Fédérale de Lausanne
David Atienza , Universidad Complutense de Madrid
Giovanni De Micheli , École Polytechnique Fédérale de Lausanne
Luca Benini , Università di Bologna
Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini, "Bringing NoCs to 65 nm", IEEE Micro, vol.27, no. 5, pp. 75-85, September/October 2007, doi:10.1109/MM.2007.79
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6. A. Pullini et al., "Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes," Proc. 18th Ann. Symp. Integrated Circuits and System Design (SBCCI 05), ACM Press, 2005, pp. 224-229.
7. S. Murali et al., "Designing Application-Specific Networks on Chips with Floorplan Information," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE Press, 2006, pp. 355-362.
8. A. Pullini et al., "NoC Design and Implementation in 65 nm Technology," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE Press, 2007, pp. 273-282.
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