The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.05 - September/October (2007 vol.27)
pp: 62-74
Anthony Chun , Intel
ABSTRACT
The SCC is a flexible and energy- and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NoC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.
INDEX TERMS
wireless, wide-area networks, communication, networking, on-chip interconnection networks, multicore architectures, parallel architectures
CITATION
David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza, "Architecture of the Scalable Communications Core's Network on Chip", IEEE Micro, vol.27, no. 5, pp. 62-74, September/October 2007, doi:10.1109/MM.2007.78
REFERENCES
1. J. Hoffman et al., "The Architecture of the Scalable Communications Core," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE CS Press, 2007, pp. 40-52.
2. T. Bjerregaard and S. Mahadevan, "A Survey of Research and Practices of Network-on-Chip," ACM Computing Surveys, vol. 38, no. 1, Mar. 2006.
3. E. Tsui et al., "A New Distributed DSP Architecture Based on the Intel IXS," Hot Chips 2002, http://www.hotchips.org/archiveshc14.
4. IEEE Std. 802.11a-1999, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, 1999.
5. IEEE Std. 802.11b-1999, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications; High-Speed Physical Layer in the 2.4 GHz Band, IEEE, 1999.
6. IEEE Std. 802.11-04/0889r6, TGn Sync Proposal Technical Specification, IEEE, May 2005.
7. IEEE P802.16e/D12, Draft IEEE Standard for Local and Metropolitan Area Networks; Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems, IEEE, Oct. 2005.
8. ETSI EN 302 304, Digital Video Broadcasting (DVB): Transmission System for Handheld Terminals (DVB-H), European Telecommunications Standards Inst, June 2004.
9. S. Vangal et al., "An 80-Tile 1.28 TLOPS Network-on-Chip in 65 nm CMOS," Proc. Int'l Conf. Solid-State Circuits (ISSCC 07), IEEE Press, 2007, pp. 98-589.
10. P. Vivet et al., "FAUST, an Asynchronous Network-on-Chip Based Architecture for Telecom Applications," http://www.date-conference.com/conference/ 2007/prog/Sessions/Session4S48.pdf.
11. H. Fujisawa et al., "Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconfigurable Logic Cores," Proc. Asian Solid-State Circuits Conf. (ASSCC 06), IEEE Press, 2006, pp. 67-70.
12. A. Chun et al., "Application of the Intel Reconfigurable Communications Architecture to 802.11a, 3G and 4G Standards," Proc. IEEE 6th Circuits and Systems Symp. Emerging Technologies, Frontiers of Mobile and Wireless Communication, IEEE Press, vol. 2, 2004, pp. 659-662.
13. Data Sheet for the ARC 605 Configurable Core, ARC International, 2005.
14. Open Core Protocol Specification 2.1, rev 1.0, OCP-IP Assoc
15. W.J. Dally and B. Towles,Principles and Practices of Interconnection Networks, Morgan Kaufman, 2004.
16. P. Mohapatra, "Wormhole Routing Techniques for Directly Connected Multicomputer Systems," ACM Computing Surveys, vol. 30, no. 3, Sept. 1998, pp. 374-410.
17. G.M. Chiu, "The Odd-Even Turn Model for Adaptive Routing," IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, July 2000, pp. 729-738.
18. C.J. Glass and L.M. Ni, "The Turn Model for Adaptive Routing," J. ACM, vol. 41, no. 5, Sept. 1994, pp. 874-902.
19. M. Pirvu, L. Bhuyan, and N. Ni, "The Impact of Link Arbitration on Switch Performance," Proc. 5th Int'l Symp. High-Performance Computer Architecture (HPCA 99), IEEE CS Press, 1999, pp. 228-235.
32 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool