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Architecture of the Scalable Communications Core's Network on Chip
September/October 2007 (vol. 27 no. 5)
pp. 62-74
The SCC is a flexible and energy- and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NoC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.

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Index Terms:
wireless, wide-area networks, communication, networking, on-chip interconnection networks, multicore architectures, parallel architectures
Citation:
David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza, "Architecture of the Scalable Communications Core's Network on Chip," IEEE Micro, vol. 27, no. 5, pp. 62-74, Sept.-Oct. 2007, doi:10.1109/MM.2007.78
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