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On-Chip Interconnection Networks of the TRIPS Chip
September/October 2007 (vol. 27 no. 5)
pp. 41-50
Paul Gratz, The University of Texas at Austin
Changkyu Kim, Intel
Karthikeyan Sankaralingam, University of Wisconsin-Madison
Premkishore Shivakumar, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

1. D. Burger et al., "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, July 2004, pp. 44-55.
2. K. Sankaralingam et al., "The Distributed Microarchitecture of the TRIPS Prototype Processor," Proc. 39th ACM/IEEE Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 480-491.
3. P. Gratz et al., "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE CS Press, 2007, pp. 7-17.
4. A.J. KleinOsowski and D.J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation Based Computer Architecture Research," Computer Architecture Letters, vol. 1, no. 1, Jan. 2002, p. 7.
5. T. Sherwood, E. Perelman, and B. Calder, "Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications," Proc. Int'l Symp. Parallel Architectures and Compilation Techniques (PACT 01), IEEE CS Press, 2001, pp. 3-15.
6. P. Gratz et al., "Implementation and Evaluation of On-Chip Network Architectures," Proc. IEEE Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, http://www.iccd-conference.org/proceedings/ 2006paper_174.pdf.
1. W. Dally and B. Towles, Principles and Practices of Interconnection Networks, 1st ed., Morgan Kaufmann, 2004.
2. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 684-689.
3. M.B. Taylor et al., "Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture," Proc. 9th Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 341-353.
4. U. Nawathe et al., "An 8-Core 64-Thread 64b Power-Efficient SPARC SoC," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 108-109, 590.
5. "Quad Core: By Popular Demand," http://www.intel.comquad-core
6. J. Dorsey et al., "An Integrated Quad-Core Opteron Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 102-103.
7. S. Vangal et al., "An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 98-99, 589.
8. D. Pham et al., "Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, Jan. 2006, pp. 179-196.
9. T. Ainsworth and T. Pinkston, "On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus," Proc. 1st ACM/IEEE Int'l Symp. Networks-on-Chip (NOCS 07), IEEE CS Press, 2007, pp. 18-29.
10. B. Khailany et al., "A Programmable 512GOPS Stream Processor for Signal, Image, and Video Processing," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 272-273, 602.
11. A. Abbo et al., "XETAL-II: A 107GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 270-271, 602.

Index Terms:
on-chip interconnection networks, multicore architectures, distributed architectures, packet-switching networks, communication, networking
Citation:
Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger, "On-Chip Interconnection Networks of the TRIPS Chip," IEEE Micro, vol. 27, no. 5, pp. 41-50, Sept.-Oct. 2007, doi:10.1109/MM.2007.90
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