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Issue No.05 - September/October (2007 vol.27)
pp: 41-50
Changkyu Kim , Intel
Karthikeyan Sankaralingam , University of Wisconsin-Madison
Premkishore Shivakumar , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Paul Gratz , The University of Texas at Austin
ABSTRACT
The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.
INDEX TERMS
on-chip interconnection networks, multicore architectures, distributed architectures, packet-switching networks, communication, networking
CITATION
Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Paul Gratz, "On-Chip Interconnection Networks of the TRIPS Chip", IEEE Micro, vol.27, no. 5, pp. 41-50, September/October 2007, doi:10.1109/MM.2007.90
REFERENCES
1. D. Burger et al., "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, July 2004, pp. 44-55.
2. K. Sankaralingam et al., "The Distributed Microarchitecture of the TRIPS Prototype Processor," Proc. 39th ACM/IEEE Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 480-491.
3. P. Gratz et al., "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE CS Press, 2007, pp. 7-17.
4. A.J. KleinOsowski and D.J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation Based Computer Architecture Research," Computer Architecture Letters, vol. 1, no. 1, Jan. 2002, p. 7.
5. T. Sherwood, E. Perelman, and B. Calder, "Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications," Proc. Int'l Symp. Parallel Architectures and Compilation Techniques (PACT 01), IEEE CS Press, 2001, pp. 3-15.
6. P. Gratz et al., "Implementation and Evaluation of On-Chip Network Architectures," Proc. IEEE Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, http://www.iccd-conference.org/proceedings/ 2006paper_174.pdf.
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