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On-Chip Interconnection Networks of the TRIPS Chip
September/October 2007 (vol. 27 no. 5)
pp. 41-50
ASCII Text
x 
 
Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger, "On-Chip Interconnection Networks of the TRIPS Chip," IEEE Micro, vol. 27, no. 5, pp. 41-50, September/October, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MM.2007.90,
author = {Paul Gratz and Changkyu Kim and Karthikeyan Sankaralingam and Heather Hanson and Premkishore Shivakumar and Stephen W. Keckler and Doug Burger},
title = {On-Chip Interconnection Networks of the TRIPS Chip},
journal ={IEEE Micro},
volume = {27},
number = {5},
issn = {0272-1732},
year = {2007},
pages = {41-50},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.90},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - On-Chip Interconnection Networks of the TRIPS Chip
IS - 5
SN - 0272-1732
SP41
EP50
EPD - 41-50
A1 - Paul Gratz,
A1 - Changkyu Kim,
A1 - Karthikeyan Sankaralingam,
A1 - Heather Hanson,
A1 - Premkishore Shivakumar,
A1 - Stephen W. Keckler,
A1 - Doug Burger,
PY - 2007
KW - on-chip interconnection networks
KW - multicore architectures
KW - distributed architectures
KW - packet-switching networks
KW - communication
KW - networking
VL - 27
JA - IEEE Micro
ER -
 
Paul Gratz, The University of Texas at Austin
Changkyu Kim, Intel
Karthikeyan Sankaralingam, University of Wisconsin-Madison
Premkishore Shivakumar, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

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Index Terms:
on-chip interconnection networks, multicore architectures, distributed architectures, packet-switching networks, communication, networking
Citation:
Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger, "On-Chip Interconnection Networks of the TRIPS Chip," IEEE Micro, vol. 27, no. 5, pp. 41-50, Sept.-Oct. 2007, doi:10.1109/MM.2007.90
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