This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Synchronization through Communication in a Massively Parallel Processor Array
September/October 2007 (vol. 27 no. 5)
pp. 32-40
Mike Butts, Ambric
Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. To ease this burden, this MPPA's architecture is based on the Structural Object Programming Model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.

1. E.A. Lee, "The Problem with Threads," Computer, vol. 39, no. 5, 2006, pp. 33-42.
2. G. Kahn, "The Semantics of a Simple Language for Parallel Programming," Information Processing, Aug. 1974, pp. 471-475.
3. M. Butts, A.M. Jones, and P. Wasson, "A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing," Proc. Ann. IEEE Symp. Field-Programmable Custom Computing Machines (FCCM 07), IEEE CS Press, 2007, pp. 55-64.
4. A.M. Jones and M. Butts, "TeraOPS Hardware: A New Massively-Parallel MIMD Computing Fabric IC," Hot Chips Symposium 18; http://www.hotchips.org/archives/hc18/2_Mon/ HC18.S5HC18.S5T1.pdf.
5. W.J. Dally et al., "The Message-Driven Processor: A Multicomputer Processing Node with Efficient Mechanisms," IEEE Micro, vol. 12, no. 2, Apr. 1992, pp. 23-39.
6. S. Borkar et al., "iWarp: An Integrated Solution to High-Speed Parallel Computing," Proc. Supercomputing, IEEE CS Press, 1988, pp. 330-339.
7. E. Caspi et al., "Stream Computations Organized for Reconfigurable Execution (SCORE)," Proc. Int'l Conf. Field-Programmable Logic and Applications (FPL 00), LNCS 1896, Springer, 2000, pp. 605-614.
8. M. Taylor et al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, vol. 22, no. 2, Mar.-Apr. 2002, pp. 25-35.
9. E. Waingold et al., "Baring It All to Software: Raw Machines," Computer, vol. 30, no. 9, Sept. 1997, pp. 86-93.
10. A. Patel et al., "A Scalable FPGA-Based Multiprocessor," Proc. Ann. IEEE Symp. Field-Programmable Custom Computing Machines (FCCM 06), IEEE CS Press, 2006, pp. 111-120.
11. C. Chang, J. Wawrzynek, and R.W. Brodersen, "BEE2: A High-End Reconfigurable Computing System," IEEE Design &Test, vol. 22, no. 2, Mar.-Apr. 2005, pp. 114-125.
12. A. Krasnov et al., "RAMP Blue: A Message-Passing Manycore System in FPGAs," Proc. Int'l Conf. Field-Programmable Logic and Applications (FPL 07), Springer, 2007.
13. P. Zuchowski et al., "A Hybrid ASIC and FPGA Architecture," Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD 02), IEEE CS Press, 2002, pp. 187-194.
1. E.A. Lee, "The Problem with Threads," Computer, vol. 39, no. 5, May 2006, pp. 33-42.
2. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer, 1999.
3. J. Ostermann et al., "Video Coding with H.264/AVC," IEEE Circuits and Systems Magazine, vol. 4, no. 1, 2004, pp. 7-28.
4. P. List et al., "Adaptive Deblocking Filter," IEEE Trans. Circuits and Systems for Video Technology, vol. 13, no. 7, July 2003, pp. 614-619.

Index Terms:
multicore architectures, multiprocessors, synchronization, multiple data stream processors, parallel architectures
Citation:
Mike Butts, "Synchronization through Communication in a Massively Parallel Processor Array," IEEE Micro, vol. 27, no. 5, pp. 32-40, Sept.-Oct. 2007, doi:10.1109/MM.2007.92
Usage of this product signifies your acceptance of the Terms of Use.