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Issue No.05 - September/October (2007 vol.27)
pp: 15-31
Liewei Bao , Tilera
Bruce Edwards , Tilera
Carl Ramey , Tilera
Anant Agarwal , Tilera
ABSTRACT
iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.
INDEX TERMS
MIMD processors, on-chip interconnection networks, multicore architectures, mesh networks, parallel architectures
CITATION
David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal, "On-Chip Interconnection Architecture of the Tile Processor", IEEE Micro, vol.27, no. 5, pp. 15-31, September/October 2007, doi:10.1109/MM.2007.89
REFERENCES
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3. M.B. Taylor et al., "Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 341-353.
4. MPI: A Message-Passing Interface Standard, Message Passing Interface Forum, 1994; http://www.mpi-forum.org/docs/mpi-11-html mpi-report.html.
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