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On-Chip Interconnection Architecture of the Tile Processor
September/October 2007 (vol. 27 no. 5)
pp. 15-31
iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

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Index Terms:
MIMD processors, on-chip interconnection networks, multicore architectures, mesh networks, parallel architectures
Citation:
David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal, "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, Sept.-Oct. 2007, doi:10.1109/MM.2007.89
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