Issue No.05 - September/October (2007 vol.27)
Thomas William Ainsworth , Northrop Grumman Space Technology
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.81
On-chip network design has become an increasingly important component of computer architecture. The Cell Broadband Engine's Element Interconnect Bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on-chip networks. To help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the EIB network using conventional latency and throughput characterization methods.
interconnection architectures, multiple data stream architectures, multicore architectures, multiprocessors, on-chip interconnection networks
Thomas William Ainsworth, "Characterizing the Cell EIB On-Chip Network", IEEE Micro, vol.27, no. 5, pp. 6-14, September/October 2007, doi:10.1109/MM.2007.81