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Issue No.04 - July/August (2007 vol.27)
pp: 34-48
Jianwei Chen , University of Southern California
Michel Dubois , University of Southern California
Per Stenström , Chalmers University of Technology
ABSTRACT
Evaluating the impact of applications with significant operating-system interactions requires detailed microarchitectural simulation combined with system-level simulation. A cost-effective and practical approach is to combine two widely used simulators. SimWattch integrates Simics, a system-level tool, with Wattch, a user-level tool, to facilitate analysis of a wider design space for computer architects and system developers.
INDEX TERMS
modeling of computer architecture, simulation, low-power design, power management
CITATION
Jianwei Chen, Michel Dubois, Per Stenström, "SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators", IEEE Micro, vol.27, no. 4, pp. 34-48, July/August 2007, doi:10.1109/MM.2007.73
REFERENCES
1. A.M. Maynard, C.M. Donnelly,, and B.R. Olszewski, "Contrasting Characteristics and Cache Performance of Technical and Multi-User Commercial Workloads," Proc. 6th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 94), ACM Press, 1994, pp. 145-156.
2. D. Brooks and V. Tiwari, M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 83-94.
3. A. Alamadeen and D. Wood, "Variability in Architectural Simulations of Multi-Threaded Workloads," Proc. 9th Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 7-18.
4. S.A. Herrod, Using Complete Machine Simulation to Understand Computer System Behavior, doctoral dissertation Stanford Univ., 1998.
5. The SPARC Architecture Manual, Version 9, SPARC International, 1992.
6. G.S. Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," IEEE Trans. Computers, vol. 39, no. 3, Mar. 1990, pp. 349-359.
7. L.A. Barroso, K. Gharachorloo, and E. Bugnion, "Memory System Characterization of Commercial Workloads," Proc. 25th Ann. Int'l Symp. Computer Architecture (ISCA 98), IEEE CS Press, 1998, pp. 3-14.
8. H.W. Cain et al., "Precise and Accurate Processor Simulations," Proc. 5th Workshop Computer Architecture Evaluation Using Commercial Workloads (CAECW 02), 2002, http://tesla.hpl.hp.com/caecw-02s1p2.pdf .
9. P.S. Magnusson et al., "SimICS/sun4m: A Virtual Workstation," Proc. Usenix Ann. Tech. Conf., Advanced Computing Systems Assoc., 1998, pp. 119-130.
10. N. Manjikian, "Parallel Simulation of Multiprocessor Execution: Implementation and Results for SimpleScalar," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS 01), IEEE Press, 2001, pp. 147-151.
11. J. Huang and D.J. Lilja, "An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor Architecture," Proc. 6th Int'l Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS 98), IEEE Press, 1998, pp. 185-191.
12. M. Torrant et al., "A Simultaneous Multithreading Simulator," ACM SIGARCH Computer Architecture News, Dec. 1999, pp. 1-5.
13. M. Ekman and P. Stenstrom, "Performance and Power Impact of Issue-Width in Chip-Multiprocessor Cores," Proc. 32nd Int'l Conf. Parallel Processing (ICPP 03), IEEE CS Press, 2003, pp. 359-368.
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