|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Li Zhao, Ravi Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Don Newell, "Exploring Large-Scale CMP Architectures Using ManySim," IEEE Micro, vol. 27, no. 4, pp. 21-33, July/August, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2007.66, author = {Li Zhao and Ravi Iyer and Jaideep Moses and Ramesh Illikkal and Srihari Makineni and Don Newell}, title = {Exploring Large-Scale CMP Architectures Using ManySim}, journal ={IEEE Micro}, volume = {27}, number = {4}, issn = {0272-1732}, year = {2007}, pages = {21-33}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.66}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Exploring Large-Scale CMP Architectures Using ManySim IS - 4 SN - 0272-1732 SP21 EP33 EPD - 21-33 A1 - Li Zhao, A1 - Ravi Iyer, A1 - Jaideep Moses, A1 - Ramesh Illikkal, A1 - Srihari Makineni, A1 - Don Newell, PY - 2007 KW - CMP KW - architecture KW - servers KW - simulation techniques KW - workload characterization KW - performance evaluation VL - 27 JA - IEEE Micro ER - | |||
1. "Intel Dual-Core Processors—The First in the Multi-core Revolution," Intel; http://www.intel.com/technology/computing dual-core.
2. S. Chaudhry et al., "High Performance Throughput Computing," IEEE Micro, vol. 25, no. 3, May-June 2005, pp. 32-45.
3. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, Mar.-Apr. 2005, pp. 21-29.
4. J. Laudon, "Performance/Watt: The New Server Focus," ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), vol. 33, no. 4, Nov. 2005, pp. 5-13, http://www.cse.ucsd.edu/~rakumar/dasCMP05 paper01.pdf.
5. M. Bohr, "Intel's 90 nm Technology: Moore's Law and More," Intel Developer Forum, Intel; ftp://download.intel.com/technology/silicon Bohr_IDF_0902.pdf.
6. R. Uhlig et al., "Intel Virtualization Technology," Computer, vol. 38, no. 5, May 2005, pp. 48-56.
7. M. Vachharajani et al., "Microarchitectural Exploration with Liberty," Proc. 35th Ann. Int'l Symp. Microarchitecture (MICRO 02), IEEE CS Press, 2002, pp. 271-282.
8. J. Emer et al., "Asim: A Performance Model Framework," Computer, vol. 35, no. 2, Feb. 2002, pp. 68-76.
9. K. Olukotun et al., "The Case for a Single-Chip Multiprocessor," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 96), ACM Press, 1996, pp. 2-11.
10. L. Hsu et al., "Exploring the Cache Design Space for Large-Scale CMPs," ACM SIGARCH Computer Architecture News, special issue: Workshop Design, Architecture and Simulation of CMP (dasCMP 05), vol. 33, no. 4, Nov. 2005, pp. 24-33, .
11. J. Moses et al., "ASPEN—Towards Effective Simulation of Threads and Engines in Evolving Platforms," Proc. 11th Int'l Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS 04), IEEE CS Press, 2004, pp. 51-58.
12. R. Kumar, V. Zyuban, and D.M. Tullsen, "Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 408-419.
13. Z. Chishti, M.D. Powell, and T.N. Vijaykumar, "Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures," Proc. 36th IEEE/ACM Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 55-67.
14. Z. Chishti, M.D. Powell, and T.N. Vijaykumar, "Optimizing Replication, Communication, and Capacity Allocation in CMPs," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 357-368.
15. R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," Proc. 18th Ann. Int'l Conf. Supercomputing (ICS 04), ACM Press, 2004, pp. 257-266.
16. E. Speight et al., "Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors," Proc. 32nd Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 346-356.

