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Issue No.03 - May/June (2007 vol.27)
pp: 49-62
David Brooks , Harvard University
Robert P. Dick , Northwestern University
Russ Joseph , Northwestern University
Li Shang , Queen's University
ABSTRACT
Power is the source of the greatest problems facing microprocessor designers. Rapid power variation brings transient errors. High power densities bring high temperatures, harming reliability and increasing leakage power. The wages of power are bulky, short-lived batteries, huge heat sinks, large on-die capacitors, high server electric bills, and unreliable microprocessors. Optimizing power depends on accurate and efficient modeling that spans different disciplines and levels, from device physics, to numerical methods, to microarchitectural design.
INDEX TERMS
modeling of computer architecture, power models, thermal analysis, reliability models, process variation
CITATION
David Brooks, Robert P. Dick, Russ Joseph, Li Shang, "Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors", IEEE Micro, vol.27, no. 3, pp. 49-62, May/June 2007, doi:10.1109/MM.2007.58
REFERENCES
1. P. Shivakumar and N.P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model, tech. report, Western Research Lab, 2001.
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