This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors
May/June 2007 (vol. 27 no. 3)
pp. 49-62
David Brooks, Harvard University
Robert P. Dick, Northwestern University
Russ Joseph, Northwestern University
Li Shang, Queen's University
Power is the source of the greatest problems facing microprocessor designers. Rapid power variation brings transient errors. High power densities bring high temperatures, harming reliability and increasing leakage power. The wages of power are bulky, short-lived batteries, huge heat sinks, large on-die capacitors, high server electric bills, and unreliable microprocessors. Optimizing power depends on accurate and efficient modeling that spans different disciplines and levels, from device physics, to numerical methods, to microarchitectural design.

1. P. Shivakumar and N.P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model, tech. report, Western Research Lab, 2001.
1. P. Shivakumar and N.P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model, tech. report, Western Research Lab, 2001.
2. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 83–94.
2. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 83–94.
3. N.S. Kim et al., "Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors," Proc. Int'l Symp. Low-Power Electronics and Design (ISLPED 04), IEEE CS Press, 2004, pp. 212–217.
3. N.S. Kim et al., "Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors," Proc. Int'l Symp. Low-Power Electronics and Design (ISLPED 04), IEEE CS Press, 2004, pp. 212–217.
4. J.A. Butts and G.S. Sohi, "A Static Power Model for Architects," Proc. Int'l Symp. Microarchitecture (MICRO 00), IEEE CS Press, 2000, pp. 191–201.
4. J.A. Butts and G.S. Sohi, "A Static Power Model for Architects," Proc. Int'l Symp. Microarchitecture (MICRO 00), IEEE CS Press, 2000, pp. 191–201.
5. W. Ye et al., "The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 340–345.
5. W. Ye et al., "The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 340–345.
6. D. Brooks et al., "New Methodology for Early-Stage, Microarchitecture-Level Power-Performance Analysis of Microprocessors," IBM J. Research and Development, vol. 47, no. 5–6, 2003, pp. 653–670.
6. D. Brooks et al., "New Methodology for Early-Stage, Microarchitecture-Level Power-Performance Analysis of Microprocessors," IBM J. Research and Development, vol. 47, no. 5–6, 2003, pp. 653–670.
7. K. Skadron et al., "Temperature-Aware Microarchitecture," Proc. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 2–13.
7. K. Skadron et al., "Temperature-Aware Microarchitecture," Proc. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 2–13.
8. P. Li et al., "Efficient Full-Chip Thermal Modeling and Analysis," Proc. Int'l Conf. Computer-Aided Design (ICCAD 04), IEEE CS Press, 2004, pp. 319–326.
8. P. Li et al., "Efficient Full-Chip Thermal Modeling and Analysis," Proc. Int'l Conf. Computer-Aided Design (ICCAD 04), IEEE CS Press, 2004, pp. 319–326.
9. Y. Yang et al., "Adaptive Multi–Domain Thermal Modeling and Analysis for Integrated Circuit Synthesis and Design," Proc. Int'l Conf. Computer–Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 575–582.
9. Y. Yang et al., "Adaptive Multi–Domain Thermal Modeling and Analysis for Integrated Circuit Synthesis and Design," Proc. Int'l Conf. Computer–Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 575–582.
10. Y. Liu et al., "Accurate Temperature–Dependent Integrated Circuit Leakage Power Estimation Is Easy," Proc. Design Automation and Test in Europe Conf. (DATE 07), IEEE CS Press, 2007, pp. 204–209.
10. Y. Liu et al., "Accurate Temperature–Dependent Integrated Circuit Leakage Power Estimation Is Easy," Proc. Design Automation and Test in Europe Conf. (DATE 07), IEEE CS Press, 2007, pp. 204–209.
11. S.S. Mukherjee et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High–Performance Microprocessor," Proc. Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 29–40.
11. S.S. Mukherjee et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High–Performance Microprocessor," Proc. Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 29–40.
12. Failure Mechanisms and Models for Semiconductor Devices, publication JEP 122–B, JEDEC, 2003.
12. Failure Mechanisms and Models for Semiconductor Devices, publication JEP 122–B, JEDEC, 2003.
13. J. Srinivasan et al., "Exploiting Structural Duplication for Lifetime Reliability Enhancement," Proc. Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 520–531.
13. J. Srinivasan et al., "Exploiting Structural Duplication for Lifetime Reliability Enhancement," Proc. Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 520–531.
14. J. Srinivasan et al., "The Impact of Technology Scaling on Lifetime Reliability," Proc. Int'l Conf. Dependable Systems and Networks (DSN 04), IEEE Press, 2004, pp. 177–186.
14. J. Srinivasan et al., "The Impact of Technology Scaling on Lifetime Reliability," Proc. Int'l Conf. Dependable Systems and Networks (DSN 04), IEEE Press, 2004, pp. 177–186.
15. W. El–Essawy and D. Albonesi, "Mitigating Inductive Noise in SMT Processors," Int'l Symp. Low–Power Electronics and Design (ISLPED 04), IEEE CS Press, 2004, pp. 332–337.
15. W. El–Essawy and D. Albonesi, "Mitigating Inductive Noise in SMT Processors," Int'l Symp. Low–Power Electronics and Design (ISLPED 04), IEEE CS Press, 2004, pp. 332–337.
16. R. Joseph, D. Brooks, and M. Martonosi, "Control Techniques to Eliminate Voltage Emergencies in High Performance Processors," Proc. 9th Int'l Symp. High–Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 79–90.
16. R. Joseph, D. Brooks, and M. Martonosi, "Control Techniques to Eliminate Voltage Emergencies in High Performance Processors," Proc. 9th Int'l Symp. High–Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 79–90.
17. M.D. Powell and T.N. Vijaykumar, "Exploiting Resonant Behavior to Reduce Inductive Noise," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 288–299.
17. M.D. Powell and T.N. Vijaykumar, "Exploiting Resonant Behavior to Reduce Inductive Noise," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 288–299.
18. D.J. Herrell and B. Beker, "Modeling of Power Distribution Systems for High–Performance Microprocessors," IEEE Trans. Advanced Packaging, vol. 22, no. 3, Aug. 1999, pp. 240–248.
18. D.J. Herrell and B. Beker, "Modeling of Power Distribution Systems for High–Performance Microprocessors," IEEE Trans. Advanced Packaging, vol. 22, no. 3, Aug. 1999, pp. 240–248.
19. I. Kantorovich et al., "Measurement of Low Impedance On Chip Power Supply Loop," IEEE Trans. Advanced Packaging, vol. 27, no. 1, Feb 2004, pp. 10–14.
19. I. Kantorovich et al., "Measurement of Low Impedance On Chip Power Supply Loop," IEEE Trans. Advanced Packaging, vol. 27, no. 1, Feb 2004, pp. 10–14.
20. M.D. Powell and T.N. Vijaykumar, "Pipeline Muffling and A Priori Current Ramping: Architectural Techniques to Reduce High–Frequency Inductive Noise," Proc. Int'l Symp. Low–Power Electronics and Design (ISLPED 03), IEEE Press, 2003, pp. 223–228.
20. M.D. Powell and T.N. Vijaykumar, "Pipeline Muffling and A Priori Current Ramping: Architectural Techniques to Reduce High–Frequency Inductive Noise," Proc. Int'l Symp. Low–Power Electronics and Design (ISLPED 03), IEEE Press, 2003, pp. 223–228.
21. S. Borkar et al., "Parameter Variations and Impact on Circuits and Microarchitecture," Proc. 40th Design Automation Conf. (DAC 03) ACM Press, 2003, p. 338.
21. S. Borkar et al., "Parameter Variations and Impact on Circuits and Microarchitecture," Proc. 40th Design Automation Conf. (DAC 03) ACM Press, 2003, p. 338.
22. P. Friedberg et al., "Modeling Within–Die Spatial Correlation Effects for Process–Design Co–optimization," Proc. 6th Int'l Symp. Quality Electronic Design (ISQED 05), IEEE Press, 2005, pp. 516–521.
22. P. Friedberg et al., "Modeling Within–Die Spatial Correlation Effects for Process–Design Co–optimization," Proc. 6th Int'l Symp. Quality Electronic Design (ISQED 05), IEEE Press, 2005, pp. 516–521.
23. A. Agarwal et al., "Path–Based Statistical Timing Analysis Using Bounds and Selective Enumeration," Proc. Int'l Workshop Timing Issues in the Specification and Synthesis of Digital Systems (TAU 02), ACM Press, 2002, pp. 16–21.
23. A. Agarwal et al., "Path–Based Statistical Timing Analysis Using Bounds and Selective Enumeration," Proc. Int'l Workshop Timing Issues in the Specification and Synthesis of Digital Systems (TAU 02), ACM Press, 2002, pp. 16–21.
24. K. Meng et al., "Modeling and Characterizing Power Variability in Multicore Architectures," IEEE Symp. Analysis of Software and Systems (ISPASS 07), IEEE Press, 2007, pp. 146–153.
24. K. Meng et al., "Modeling and Characterizing Power Variability in Multicore Architectures," IEEE Symp. Analysis of Software and Systems (ISPASS 07), IEEE Press, 2007, pp. 146–153.
25. E. Humenay, D. Tarjan, and K. Skadron, "Impact of Parameter Variations on Multi–core Chips," Proc. Workshop Architectural Support for Gigascale Integration (ASGI 06), 2006, http://www.cs.virginia.edu/~skadron/Papers PV_asgi06.pdf.
25. E. Humenay, D. Tarjan, and K. Skadron, "Impact of Parameter Variations on Multi–core Chips," Proc. Workshop Architectural Support for Gigascale Integration (ASGI 06), 2006, http://www.cs.virginia.edu/~skadron/Papers PV_asgi06.pdf.
26. S.R. Nassif, "Modeling and Forecasting of Manufacturing Variations," Proc. 5th Int'l Workshop Statistical Metrology, IEEE Press, 2000, pp. 2–10.
26. S.R. Nassif, "Modeling and Forecasting of Manufacturing Variations," Proc. 5th Int'l Workshop Statistical Metrology, IEEE Press, 2000, pp. 2–10.
27. K.A. Bowman, S.G. Duvall, and J.D. Meindl, "Impact of Die–to–Die and Within–Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183–190.
27. K.A. Bowman, S.G. Duvall, and J.D. Meindl, "Impact of Die–to–Die and Within–Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183–190.
28. B.F. Romanescu, S. Ozev, and D.J. Sorin, "Quantifying the Impact of Process Variability on Microprocessor Behavior," Proc. Workshop Architectural Reliability (WAR 06), 2006, http://www.ee.duke.edu/~sorin/paperswar06_variability.pdf .
28. B.F. Romanescu, S. Ozev, and D.J. Sorin, "Quantifying the Impact of Process Variability on Microprocessor Behavior," Proc. Workshop Architectural Reliability (WAR 06), 2006, http://www.ee.duke.edu/~sorin/paperswar06_variability.pdf .

Index Terms:
modeling of computer architecture, power models, thermal analysis, reliability models, process variation
Citation:
David Brooks, Robert P. Dick, Russ Joseph, Li Shang, "Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors," IEEE Micro, vol. 27, no. 3, pp. 49-62, May-June 2007, doi:10.1109/MM.2007.58
Usage of this product signifies your acceptance of the Terms of Use.