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Issue No.03 - May/June (2007 vol.27)
pp: 31-48
Gabriel H. Loh , Georgia Institute of Technology
Yuan Xie , Pennsylvania State University
Bryan Black , Intel
ABSTRACT
Three-dimensional die-stacking integration stacks multiple layers of processed silicon with a very high-density, low-latency layer-to-layer interconnect. After presenting a brief background on 3D die-stacking technology, this article gives multiple case studies on different approaches for implementing single-core and multicore 3D processors and discusses how to design future microprocessors given this emerging technology.
INDEX TERMS
processor architectures, computer systems organization, 3D integration
CITATION
Gabriel H. Loh, Yuan Xie, Bryan Black, "Processor Design in 3D Die-Stacking Technologies", IEEE Micro, vol.27, no. 3, pp. 31-48, May/June 2007, doi:10.1109/MM.2007.59
REFERENCES
1. S. Das et al., "Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits," Proc. Int'l Symp. Physical Design (ISPD 04), ACM Press, 2004, pp. 108-115.
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