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Processor Design in 3D Die-Stacking Technologies
May/June 2007 (vol. 27 no. 3)
pp. 31-48
Gabriel H. Loh, Georgia Institute of Technology
Yuan Xie, Pennsylvania State University
Bryan Black, Intel
Three-dimensional die-stacking integration stacks multiple layers of processed silicon with a very high-density, low-latency layer-to-layer interconnect. After presenting a brief background on 3D die-stacking technology, this article gives multiple case studies on different approaches for implementing single-core and multicore 3D processors and discusses how to design future microprocessors given this emerging technology.

1. S. Das et al., "Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits," Proc. Int'l Symp. Physical Design (ISPD 04), ACM Press, 2004, pp. 108-115.
1. S. Das et al., "Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits," Proc. Int'l Symp. Physical Design (ISPD 04), ACM Press, 2004, pp. 108-115.
2. F. Arnaud et al., "A Functional 0.69 μm2 Embedded 6T-SRAM Bit Cell for 65nm CMOS Platform," Proc. 19th Symp. VLSI Technology, IEEE Press, 2003, pp. 342-351.
2. F. Arnaud et al., "A Functional 0.69 μm2 Embedded 6T-SRAM Bit Cell for 65nm CMOS Platform," Proc. 19th Symp. VLSI Technology, IEEE Press, 2003, pp. 342-351.
3. Y. Cao et al., "New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design," Proc. 2000 Custom Integrated Circuits Conf. (CICC 00), IEEE Press, 2000, pp. 201-204.
3. Y. Cao et al., "New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design," Proc. 2000 Custom Integrated Circuits Conf. (CICC 00), IEEE Press, 2000, pp. 201-204.
4. K. Puttaswamy and G.H. Loh , "Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology," Proc. Int'l Symp. VLSI (ISVLSI 06), IEEE CS Press, 2006, pp. 384-389.
4. K. Puttaswamy and G.H. Loh, "Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology," Proc. Int'l Symp. VLSI (ISVLSI 06), IEEE CS Press, 2006, pp. 384-389.
5. K. Puttaswamy and G.H. Loh , "Implementing Caches in a 3D Technology for High Performance Processors," Proc. Int'l Conf. Computer Design (ICCD 05), IEEE CS Press, 2005, pp. 525-532.
5. K. Puttaswamy and G.H. Loh, "Implementing Caches in a 3D Technology for High Performance Processors," Proc. Int'l Conf. Computer Design (ICCD 05), IEEE CS Press, 2005, pp. 525-532.
6. P. Reed , G. Yeung , and B. Black , "Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology," Proc. Int'l Conf. Integrated Circuit Design and Technology (ICICDT 05), IEEE Press, 2005, pp. 15-18.
6. P. Reed, G. Yeung, and B. Black, "Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology," Proc. Int'l Conf. Integrated Circuit Design and Technology (ICICDT 05), IEEE Press, 2005, pp. 15-18.
7. Y.-F Tsai et al., "Three-Dimensional Cache Design Using 3DCacti," Proc. Int'l Conf. Computer Design (ICCD 05), IEEE CS Press, 2005, pp. 519-524.
7. Y.-F Tsai et al., "Three-Dimensional Cache Design Using 3DCacti," Proc. Int'l Conf. Computer Design (ICCD 05), IEEE CS Press, 2005, pp. 519-524.
8. Y. Xie et al., "Design Space Exploration for 3D Architecture," ACM J. Emerging Technologies in Computer Systems, vol. 2, no. 2, Apr 2006, pp. 65-103.
8. Y. Xie et al., "Design Space Exploration for 3D Architecture," ACM J. Emerging Technologies in Computer Systems, vol. 2, no. 2, Apr 2006, pp. 65-103.
9. G. Schrom et al., "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 04), IEEE Press, 2004, pp. 263-268.
9. G. Schrom et al., "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 04), IEEE Press, 2004, pp. 263-268.
10. G. Hinton et al., "The Microarchitecture of the Pentium 4 Processor," Intel Technology J, Q1 2001, ftp://download.intel.com/technology/itj/ q12001/pdfart_2.pdf.
10. G. Hinton et al., "The Microarchitecture of the Pentium 4 Processor," Intel Technology J, Q1 2001, ftp://download.intel.com/technology/itj/ q12001/pdfart_2.pdf.
11. D. Boggs et al., "The Microarchitecture of the Pentium 4 Processor on 90nm Technology," Intel Technology J, vol. 8, no. 1.
11. D. Boggs et al., "The Microarchitecture of the Pentium 4 Processor on 90nm Technology," Intel Technology J, vol. 8, no. 1.
12. S. Palacharla , Complexity-Effective Superscalar Processors, doctoral thesis Dept. of Computer Science, Univ. of Wisconsin, 1998.
12. S. Palacharla, Complexity-Effective Superscalar Processors, doctoral thesis Dept. of Computer Science, Univ. of Wisconsin, 1998.
13. C. Kim et al., "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," Proc. 10th Symp. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 211-222.
13. C. Kim et al., "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," Proc. 10th Symp. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 211-222.
14. F. Li et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," Proc. 33rd Int'l Symp. Computer Architecture (ISCA 06), IEEE CS Press, 2006, pp. 130-141.
14. F. Li et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," Proc. 33rd Int'l Symp. Computer Architecture (ISCA 06), IEEE CS Press, 2006, pp. 130-141.
15. P. Dubey , "Recognition, Mining and Synthesis Moves Computers to the Era of Tera," Technology@Intel Magazine, 2005, http://www.intel.com/technology/magazine/ computingrecognition-mining-synthesis-0205.pdf .
15. P. Dubey, "Recognition, Mining and Synthesis Moves Computers to the Era of Tera," Technology@Intel Magazine, 2005, http://www.intel.com/technology/magazine/ computingrecognition-mining-synthesis-0205.pdf .

Index Terms:
processor architectures, computer systems organization, 3D integration
Citation:
Gabriel H. Loh, Yuan Xie, Bryan Black, "Processor Design in 3D Die-Stacking Technologies," IEEE Micro, vol. 27, no. 3, pp. 31-48, May-June 2007, doi:10.1109/MM.2007.59
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