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Processor Design in 3D Die-Stacking Technologies
May/June 2007 (vol. 27 no. 3)
pp. 31-48
ASCII Text
x 
 
Gabriel H. Loh, Yuan Xie, Bryan Black, "Processor Design in 3D Die-Stacking Technologies," IEEE Micro, vol. 27, no. 3, pp. 31-48, May/June, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MM.2007.59,
author = {Gabriel H. Loh and Yuan Xie and Bryan Black},
title = {Processor Design in 3D Die-Stacking Technologies},
journal ={IEEE Micro},
volume = {27},
number = {3},
issn = {0272-1732},
year = {2007},
pages = {31-48},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.59},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Processor Design in 3D Die-Stacking Technologies
IS - 3
SN - 0272-1732
SP31
EP48
EPD - 31-48
A1 - Gabriel H. Loh,
A1 - Yuan Xie,
A1 - Bryan Black,
PY - 2007
KW - processor architectures
KW - computer systems organization
KW - 3D integration
VL - 27
JA - IEEE Micro
ER -
 
Gabriel H. Loh, Georgia Institute of Technology
Yuan Xie, Pennsylvania State University
Bryan Black, Intel
Three-dimensional die-stacking integration stacks multiple layers of processed silicon with a very high-density, low-latency layer-to-layer interconnect. After presenting a brief background on 3D die-stacking technology, this article gives multiple case studies on different approaches for implementing single-core and multicore 3D processors and discusses how to design future microprocessors given this emerging technology.

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Index Terms:
processor architectures, computer systems organization, 3D integration
Citation:
Gabriel H. Loh, Yuan Xie, Bryan Black, "Processor Design in 3D Die-Stacking Technologies," IEEE Micro, vol. 27, no. 3, pp. 31-48, May-June 2007, doi:10.1109/MM.2007.59
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