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Transactional Memory: An Overview
May/June 2007 (vol. 27 no. 3)
pp. 8-29
Tim Harris, Microsoft Research
Adrián Cristal, Barcelona Supercomputing Center
Osman S. Unsal, Barcelona Supercomputing Center
Eduard Ayguade, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya
Fabrizio Gagliardi, Microsoft
Burton Smith, Microsoft
Mateo Valero, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya
Writing applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ones. This article presents a survey of transactional memory, a mechanism that promises to enable scalable performance while freeing programmers from some of the burden of modifying their parallel code.

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Index Terms:
transactional memory, memory architecture, multithreading, parallel programming
Citation:
Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguade, Fabrizio Gagliardi, Burton Smith, Mateo Valero, "Transactional Memory: An Overview," IEEE Micro, vol. 27, no. 3, pp. 8-29, May-June 2007, doi:10.1109/MM.2007.63
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