Issue No.02 - March/April (2007 vol.27)
Pat Conway , Advanced Micro Devices
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.43
To increase performance while operating within a fixed power budget, the AMD Opteron processor integrates multiple x86-64 cores with a router and memory controller. AMD's experience with building a wide variety of system topologies using Opteron's HyperTransport-based processor interface has provided useful lessons that expose the challenges to be addressed when designing future system interconnect, memory hierarchy, and I/O to scale with both the number of cores and sockets in future x86-64 CMP architectures.
system topology, northbridge, microarchitecture, scalability, point-to-point networking
Pat Conway, "The AMD Opteron Northbridge Architecture", IEEE Micro, vol.27, no. 2, pp. 10-21, March/April 2007, doi:10.1109/MM.2007.43