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Issue No.02 - March/April (2007 vol.27)
pp: 4-5
Published by the IEEE Computer Society
David H. Albonesi , Cornell University
ABSTRACT
Despite the move away from very high-frequency, high-ILP cores to multiple, more modest cores ("multicore"), power is still a huge, unsolved problem for the microprocessor industry. The emphasis is no longer power-aware processor microarchitecture but power-aware systems architecture. The "system" extends from the multicore system-on-chip to the external memory, disks, indeed to the entire enterprise. The data center has arisen as a major target of power-related computer architecture research. The greater question is, in our attempts to make the world's information available to all in the blink of an eye, what is the environmental cost, and how can we as a research community address this problem?
When the first Hot Chips conference was held in 1989, a boast that your chip was "hot" was perhaps accompanied by chest-thumping performance claims. A look back at that conference confirms that at the time microprocessors were primarily about performance within a given market segment cost. Those of you who have been around as long as I have will recognize that when you have "ECL" or "GaAs" in the title of your presentation—as was the case in two presentations in the first session of Hot Chips 1—you are projecting "high performance" on to your audience. Of course, as the guest editors of this Hot Chips 18 issue of IEEE Micro point out, the landscape is vastly different today. No chip manufacturer wants to have a "hot" chip in the literal sense—one that drains the life from your battery, that can't be efficiently cooled, or that runs up the electricity bill at a data center. Today, a truly hot chip is a calling card for project cancellation.
Yet, research in power-aware microprocessor architecture appears to have cooled off (pun intended) in recent years. Table 1 shows (based on my unscientific, 20–minute exercise, subject to interpretation) the number of power-related papers presented each year since 1999 at the International Symposium on Microarchitecture, and since 2000 at the International Symposium on Computer Architecture. In his keynote address at MICRO 1999, Intel vice president Fred Pollack introduced his infamous graph showing that microprocessor power density would by now have surpassed the level of a nuclear reactor. Of course, such chips would be impractical for commodity systems, and that was precisely the point: Times were getting desperate, and we needed to take action quickly. I had one of the two power-related papers in that conference (the other was by Enric Musoll of XStream Logic), but as the table shows, the number of power-aware microarchitecture papers steadily increased thereafter. In fact, although I consider my MICRO 1999 paper a pretty modest technical contribution, it's by far my most-cited publication because of the surge in power-related activity that followed that conference. Many MICRO and ISCA keynotes in the next few years also emphasized the power problem.

Table 1. Power-aware microarchitecture papers in MICRO and ISCA conferences, 1999 to present.


A look at Table 1 reveals that power-aware microarchitecture activity (as measured by the number of such papers appearing in MICRO and ISCA) peaked in 2003, and has declined since then. I've noticed that many of us who used to boldly proclaim ourselves as working on "power-aware microprocessor architectures" now place that phrase farther down on our list of research interests.
Perhaps there's a perception within our community that the move away from very high-frequency, high-ILP cores to multiple, more modest cores ("multicore") has solved the power problem. The multicore approach certainly guards against the dramatic increases in power density projected by Fred Pollack in 1999, but is the power problem solved?
Not so, according to the industry leaders that I talked to in preparing this message. I'll have more about their comments in the next issue of Micro, but suffice it to say that power is still a huge, unsolved problem for the microprocessor industry.
So, if microprocessor power remains a major concern, even with the shift to multicore designs, why the apparent drop-off in interest? Some of this is due to the natural progression from one research topic to the next, but other forces are at work. From the academic standpoint, it's no longer a no-brainer to dedicate resources (funding, graduate students, personal time) to power-aware processor microarchitecture research. A lot of low-hanging fruit has been picked in the area of processor core and caches, so it's much more difficult to come up with unique approaches. Power-aware processor microarchitecture is now mainstream, and so a funding proposal in the area might not garner the interest that it used to. And the bar of acceptance for power-aware microarchitecture papers is much higher at conferences like MICRO and ISCA. I have to admit that for me the bar is quite high when a power-aware issue queue or cache paper comes to me for review. Those areas are so picked over that virtually all papers that I review in those areas have a strong tie to prior work.
Although research in power-aware computer architecture is still vital to the industry, the emphasis is no longer power-aware processor microarchitecture but power-aware systems architecture. The "system" extends from the multicore system-on-chip to the external memory, disks, indeed to the entire enterprise. You'll find three clearly power-related computer architecture papers in ISCA this year, two on main memory power and the third on power provisioning in the data center (there is a fourth on validating power models). The data center has arisen as a major target of power-related computer architecture research in recent years, and for good reason. A new data center requires a multimillion-dollar initial infrastructure investment, and a multimillion-dollar yearly operating budget, for power delivery and cooling. With so much of the cost of building and operating a data center related to power, why are many of us still primarily optimizing for workloads like SPEC CPU? The greater question is, in our attempts to make the world's information available to all in the blink of an eye, what is the environmental cost, and how can we as a research community address this problem? I'll have more on these topics in the next issue.
On a final note, I wish to thank our guest editors and the IEEE Micro staff for their terrific job in putting together this year's Hot Chips issue. Because the Hot Chips conference proceedings consists of only talk slides and abstracts, IEEE Micro Hot Chips articles are written from scratch (unlike the Top Picks issue, for which the articles are derived from conference papers). Therefore, it takes a dedicated, collective effort on behalf of the authors, editors, reviewers, and staff to put together the Hot Chips issue. I sincerely hope you enjoy, and learn from, this year's selections.
I always welcome your feedback at albonesi@csl.cornell.edu.
David H.Albonesi
Editor in Chief
IEEE Micro
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