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A Top-Down Approach to Architecting CPI Component Performance Counters
January/February 2007 (vol. 27 no. 1)
pp. 84-93
Stijn Eyerman, Ghent University
Lieven Eeckhout, Ghent University
Tejas Karkhanis, Advanced Micro Devices
James E. Smith, University of Wisconsin-Madison
Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various miss events. Constructing accurate CPI components for out-of-order superscalar processors is complicated, however, because computation and miss event handling overlap. The authors' counter architecture, using an analytical superscalar performance model, handles overlap effects more accurately than existing methods.
Index Terms:
experimentation, measurement, performance, modeling techniques, hardware performance counter architecture, superscalar processor performance modeling
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, "A Top-Down Approach to Architecting CPI Component Performance Counters," IEEE Micro, vol. 27, no. 1, pp. 84-93, Jan.-Feb. 2007, doi:10.1109/MM.2007.3
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