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Leveraging Wire Properties at the Microarchitecture Level
November/December 2006 (vol. 26 no. 6)
pp. 40-52
| ASCII Text | x | ||
| Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter, "Leveraging Wire Properties at the Microarchitecture Level," IEEE Micro, vol. 26, no. 6, pp. 40-52, November/December, 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2006.123, author = {Rajeev Balasubramonian and Naveen Muralimanohar and Karthik Ramani and Liqun Cheng and John B. Carter}, title = {Leveraging Wire Properties at the Microarchitecture Level}, journal ={IEEE Micro}, volume = {26}, number = {6}, issn = {0272-1732}, year = {2006}, pages = {40-52}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.123}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Leveraging Wire Properties at the Microarchitecture Level IS - 6 SN - 0272-1732 SP40 EP52 EPD - 40-52 A1 - Rajeev Balasubramonian, A1 - Naveen Muralimanohar, A1 - Karthik Ramani, A1 - Liqun Cheng, A1 - John B. Carter, PY - 2006 KW - interconnections KW - advanced technologies KW - energy-aware systems KW - interconnection architectures KW - interprocessor communications KW - multiprocessor systems VL - 26 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.123
In future microprocessors, communication will emerge as the major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy.
Index Terms:
interconnections, advanced technologies, energy-aware systems, interconnection architectures, interprocessor communications, multiprocessor systems
Citation:
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter, "Leveraging Wire Properties at the Microarchitecture Level," IEEE Micro, vol. 26, no. 6, pp. 40-52, Nov.-Dec. 2006, doi:10.1109/MM.2006.123
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