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Leveraging Wire Properties at the Microarchitecture Level
November/December 2006 (vol. 26 no. 6)
pp. 40-52
Rajeev Balasubramonian, University of Utah
Naveen Muralimanohar, University of Utah
Karthik Ramani, University of Utah
Liqun Cheng, University of Utah
John B. Carter, University of Utah
In future microprocessors, communication will emerge as the major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy.
Index Terms:
interconnections, advanced technologies, energy-aware systems, interconnection architectures, interprocessor communications, multiprocessor systems
Citation:
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter, "Leveraging Wire Properties at the Microarchitecture Level," IEEE Micro, vol. 26, no. 6, pp. 40-52, Nov.-Dec. 2006, doi:10.1109/MM.2006.123
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