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Designing a Crossbar Scheduler for HPC Applications
May/June 2006 (vol. 26 no. 3)
pp. 58-71
Cyriel Minkenberg, IBM Zurich Research Laboratory
Fran?ois Abel, IBM Zurich Research Laboratory
Peter M?, IBM Zurich Research Laboratory
Raj Krishnamurthy, IBM Zurich Research Laboratory
Mitchell Gusat, IBM Zurich Research Laboratory
Peter Dill, IBM Zurich Research Laboratory
Ilias Iliadis, IBM Zurich Research Laboratory
Ronald Luijten, IBM Zurich Research Laboratory
B. Roe Hemenway, Corning Inc.
Richard Grzybowski, Corning Inc.
Enrico Schiattarella, Politecnico di Torino
A crucial part of any high-performance computing (HPC) system is its interconnection network. Corning and IBM are jointly developing a demonstration interconnect based on optical cell swtiching with electronic control. Key innovations in the scheduler architecture directly address the main HPC requirements: low latency, high throughput, efficient multicast suppot, and high reliability.
Index Terms:
high-performance computing, crossbar scheduler, interconnection network
Citation:
Cyriel Minkenberg, Fran?ois Abel, Peter M?, Raj Krishnamurthy, Mitchell Gusat, Peter Dill, Ilias Iliadis, Ronald Luijten, B. Roe Hemenway, Richard Grzybowski, Enrico Schiattarella, "Designing a Crossbar Scheduler for HPC Applications," IEEE Micro, vol. 26, no. 3, pp. 58-71, May-June 2006, doi:10.1109/MM.2006.51
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