This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
SeaStar Interconnect: Balanced Bandwidth for Scalable Performance
May/June 2006 (vol. 26 no. 3)
pp. 41-57
Ron Brightwell, Sandia National Laboratories
Kevin T. Pedretti, Sandia National Laboratories
Keith D. Underwood, Sandia National Laboratories
Trammell Hudson, OS Research
The SeaStar, a new ASIC from Cray, is a full system-on-chip design that integrates high-speed serial links, a 3D router, and traditional network interface functionality, including an embedded processor in a single chip.
Index Terms:
Cray SeaStar, inteconnect, system-on-chip
Citation:
Ron Brightwell, Kevin T. Pedretti, Keith D. Underwood, Trammell Hudson, "SeaStar Interconnect: Balanced Bandwidth for Scalable Performance," IEEE Micro, vol. 26, no. 3, pp. 41-57, May-June 2006, doi:10.1109/MM.2006.65
Usage of this product signifies your acceptance of the Terms of Use.