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SeaStar Interconnect: Balanced Bandwidth for Scalable Performance
May/June 2006 (vol. 26 no. 3)
pp. 41-57
| ASCII Text | x | ||
| Ron Brightwell, Kevin T. Pedretti, Keith D. Underwood, Trammell Hudson, "SeaStar Interconnect: Balanced Bandwidth for Scalable Performance," IEEE Micro, vol. 26, no. 3, pp. 41-57, May/June, 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2006.65, author = {Ron Brightwell and Kevin T. Pedretti and Keith D. Underwood and Trammell Hudson}, title = {SeaStar Interconnect: Balanced Bandwidth for Scalable Performance}, journal ={IEEE Micro}, volume = {26}, number = {3}, issn = {0272-1732}, year = {2006}, pages = {41-57}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.65}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - SeaStar Interconnect: Balanced Bandwidth for Scalable Performance IS - 3 SN - 0272-1732 SP41 EP57 EPD - 41-57 A1 - Ron Brightwell, A1 - Kevin T. Pedretti, A1 - Keith D. Underwood, A1 - Trammell Hudson, PY - 2006 KW - Cray SeaStar KW - inteconnect KW - system-on-chip VL - 26 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.65
The SeaStar, a new ASIC from Cray, is a full system-on-chip design that integrates high-speed serial links, a 3D router, and traditional network interface functionality, including an embedded processor in a single chip.
Index Terms:
Cray SeaStar, inteconnect, system-on-chip
Citation:
Ron Brightwell, Kevin T. Pedretti, Keith D. Underwood, Trammell Hudson, "SeaStar Interconnect: Balanced Bandwidth for Scalable Performance," IEEE Micro, vol. 26, no. 3, pp. 41-57, May-June 2006, doi:10.1109/MM.2006.65
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