Issue No.03 - May/June (2006 vol.26)
Michael Kistler , IBM Austin Research Laboratory
Fabrizio Petrini , Pacific Northwest National Laboratory
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.49
Multicore designs promise various power-performance and area-performance benefits. But inadequate design of the on-chip communication network can deprive applications of these benefits. To illuminate this important point in multicore processor design, the authors analyze the Cell processor's communication network, using a series of benchmarks involving DMA traffic patterns and synchronization protocols.
Cell Broadband Engine processor, multiprocessor communication network
Michael Kistler, Fabrizio Petrini, "Cell Multiprocessor Communication Network: Built for Speed", IEEE Micro, vol.26, no. 3, pp. 10-23, May/June 2006, doi:10.1109/MM.2006.49