Issue No.02 - March/April (2006 vol.26)
Saibal Mukhopadhyay , Purdue University
Arijit Raychowdhury , Purdue University
Amit Agarwal , Intel Corp.
Chris H. Kim , University of Minnesota
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.39
Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.
leakage power reduction, nanoscale circuits, CMOS, technology scaling
Saibal Mukhopadhyay, Arijit Raychowdhury, Amit Agarwal, Chris H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits", IEEE Micro, vol.26, no. 2, pp. 68-80, March/April 2006, doi:10.1109/MM.2006.39