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Leakage Power Analysis and Reduction for Nanoscale Circuits
March/April 2006 (vol. 26 no. 2)
pp. 68-80
Amit Agarwal, Intel Corp.
Saibal Mukhopadhyay, Purdue University
Arijit Raychowdhury, Purdue University
Kaushik Roy, Purdue University
Chris H. Kim, University of Minnesota
Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.
Index Terms:
leakage power reduction, nanoscale circuits, CMOS, technology scaling
Citation:
Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits," IEEE Micro, vol. 26, no. 2, pp. 68-80, March-April 2006, doi:10.1109/MM.2006.39
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