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Synergistic Processing in Cell's Multicore Architecture
March/April 2006 (vol. 26 no. 2)
pp. 10-24
| ASCII Text | x | ||
| Michael Gschwind, H. Peter Hofstee, Brian Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki, "Synergistic Processing in Cell's Multicore Architecture," IEEE Micro, vol. 26, no. 2, pp. 10-24, March/April, 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2006.41, author = {Michael Gschwind and H. Peter Hofstee and Brian Flachs and Martin Hopkins and Yukio Watanabe and Takeshi Yamazaki}, title = {Synergistic Processing in Cell's Multicore Architecture}, journal ={IEEE Micro}, volume = {26}, number = {2}, issn = {0272-1732}, year = {2006}, pages = {10-24}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.41}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Synergistic Processing in Cell's Multicore Architecture IS - 2 SN - 0272-1732 SP10 EP24 EPD - 10-24 A1 - Michael Gschwind, A1 - H. Peter Hofstee, A1 - Brian Flachs, A1 - Martin Hopkins, A1 - Yukio Watanabe, A1 - Takeshi Yamazaki, PY - 2006 KW - synergistic processing KW - Cell Broadband Engine KW - multicore architecture VL - 26 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.41
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.
Index Terms:
synergistic processing, Cell Broadband Engine, multicore architecture
Citation:
Michael Gschwind, H. Peter Hofstee, Brian Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki, "Synergistic Processing in Cell's Multicore Architecture," IEEE Micro, vol. 26, no. 2, pp. 10-24, March-April 2006, doi:10.1109/MM.2006.41
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