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Synergistic Processing in Cell's Multicore Architecture
March/April 2006 (vol. 26 no. 2)
pp. 10-24
Yukio Watanabe, Toshiba
Takeshi Yamazaki, Sony Computer Entertainment
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.
Index Terms:
synergistic processing, Cell Broadband Engine, multicore architecture
Citation:
Michael Gschwind, H. Peter Hofstee, Brian Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki, "Synergistic Processing in Cell's Multicore Architecture," IEEE Micro, vol. 26, no. 2, pp. 10-24, March-April 2006, doi:10.1109/MM.2006.41
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