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Energy-Efficient Thread-Level Speculation
January/February 2006 (vol. 26 no. 1)
pp. 80-91
Jose Renau, University of California at Santa Cruz
Karin Strauss, University of Illinois at Urbana-Champaign
Luis Ceze, University of Illinois at Urbana-Champaign
Wei Liu, University of Illinois at Urbana-Champaign
Smruti R. Sarangi, University of Illinois at Urbana-Champaign
James Tuck, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.
Index Terms:
Thread-level speculation, chip multiprocessors, out-of-order task spawning
Citation:
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas, "Energy-Efficient Thread-Level Speculation," IEEE Micro, vol. 26, no. 1, pp. 80-91, Jan.-Feb. 2006, doi:10.1109/MM.2006.11
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