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Issue No.01 - January/February (2006 vol.26)
pp: 40-47
Ronald D. Barnes , George Mason University
Shane Ryoo , University of Illinois, Urbana-Champaign
Wen-mei W. Hwu , University of Illinois, Urbana-Champaign
ABSTRACT
Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.
INDEX TERMS
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design
CITATION
Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu, "Tolerating Cache-Miss Latency with Multipass Pipelines", IEEE Micro, vol.26, no. 1, pp. 40-47, January/February 2006, doi:10.1109/MM.2006.25
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