Issue No.01 - January/February (2006 vol.26)
Ibrahim Hur , IBM Corp. and The University of Texas at Austin
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.1
Careful memory scheduling can increase memory bandwidth and overall system performance. We present a new memory scheduler that makes decisions based on the history of recently scheduled operations, providing two advantages: It can better reason about the delays associated with complex DRAM structure, and it can adapt to different observed workload.
Memory schedulers, memory bandwidth, processors, DRAM, IBM Power5
Ibrahim Hur, "Adaptive History-Based Memory Schedulers for Modern Processors", IEEE Micro, vol.26, no. 1, pp. 22-29, January/February 2006, doi:10.1109/MM.2006.1