Issue No.01 - January/February (2006 vol.26)
Onur Mutlu , University of Texas at Austin
Hyesoon Kim , University of Texas at Austin
Yale N. Patt , University of Texas at Austin
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.10
Several simple techniques can make runahead execution more efficient by reducing the number of instructions executed and thereby reducing the additional energy consumption typically associated with runahead execution.
Runahead execution, memory latency tolerance, processors
Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance", IEEE Micro, vol.26, no. 1, pp. 10-20, January/February 2006, doi:10.1109/MM.2006.10