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Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
January/February 2006 (vol. 26 no. 1)
pp. 10-20
Onur Mutlu, University of Texas at Austin
Hyesoon Kim, University of Texas at Austin
Yale N. Patt, University of Texas at Austin
Several simple techniques can make runahead execution more efficient by reducing the number of instructions executed and thereby reducing the additional energy consumption typically associated with runahead execution.
Index Terms:
Runahead execution, memory latency tolerance, processors
Citation:
Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," IEEE Micro, vol. 26, no. 1, pp. 10-20, Jan.-Feb. 2006, doi:10.1109/MM.2006.10
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