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An Experimental Study of Soft Errors in Microprocessors
November/December 2005 (vol. 25 no. 6)
pp. 30-39
Giacinto P. Saggese, University of Illinois, Urbana-Champaign
Nicholas J. Wang, University of Illinois, Urbana-Champaign
Zbigniew T. Kalbarczyk, University of Illinois, Urbana-Champaign
Sanjay J. Patel, University of Illinois, Urbana-Champaign
Ravishankar K. Iyer, University of Illinois, Urbana-Champaign
The issue of soft errors is an important emerging concern in the design and implementation of future microprocessors. To date, in all but the most mission-critical applications, implementing parity and Error Correction Codes for caches and other large, regular SRAM structures has been sufficient to stem the growing soft error tide. However, this may not be the case for long, and questions remain as to efficient methods to detect and recover from soft errors ? in particular errors in the less structured execution sections. In this work, we examine the impact of soft errors on two different microarchitectures: a simple 5-stage DLX processor and high-performance implementation of an Alpha processor. The results contrast impact of soft errors on combinational and sequential logic, identify the most vulnerable units, and assess the impact of soft errors on the application.
Index Terms:
Soft errors, Microprocessor Architecture, Fault Injection, Soft error sensitivity, Assessment and Protection Techniques
Citation:
Giacinto P. Saggese, Nicholas J. Wang, Zbigniew T. Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer, "An Experimental Study of Soft Errors in Microprocessors," IEEE Micro, vol. 25, no. 6, pp. 30-39, Nov.-Dec. 2005, doi:10.1109/MM.2005.104
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