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Formal Control Techniques for Power-Performance Management
September/October 2005 (vol. 25 no. 5)
pp. 52-62
Qiang Wu, Princeton University
Philo Juang, Princeton University
Margaret Martonosi, Princeton University
Li-Shiuan Peh, Princeton University
Douglas W. Clark, Princeton University
These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.
Index Terms:
Power performance management, dynamic voltage, frequency sealing, multiple-clock-domain, chip multiprocessors
Citation:
Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark, "Formal Control Techniques for Power-Performance Management," IEEE Micro, vol. 25, no. 5, pp. 52-62, Sept.-Oct. 2005, doi:10.1109/MM.2005.87
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