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QsNetII: Defining High-Performance Network Design
July/August 2005 (vol. 25 no. 4)
pp. 34-47
Jon Beecroft, Quadrics
David Addison, Quadrics
David Hewson, Quadrics
Moray McLaren, Quadrics
Duncan Roweth, Quadrics
Fabrizio Petrini, Pacific Northwest National Laboratory
Jarek Nieplocha, Pacific Northwest National Laboratory
QsNetII optimizes interprocessor communication in systems built from standard server building blocks. Its short-message processing unit permits fast injection of small messages, providing ultra-low latency and scalability to thousands of nodes.
Index Terms:
Microprocessors and microcomputers, Network connectivity chips, Supercomputers, Clusters of Workstations, Communication Protocols
Citation:
Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha, "QsNetII: Defining High-Performance Network Design," IEEE Micro, vol. 25, no. 4, pp. 34-47, July-Aug. 2005, doi:10.1109/MM.2005.75
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