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Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories
July/August 2005 (vol. 25 no. 4)
pp. 20-32
Yen-Jen Chang, National Chung-Hsing University
Feipei Lai, National Taiwan University
A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip's total power consumption. Because most bit values read from the cache are 0s, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.
Index Terms:
Cache, Dynamic zero-sensitivity, Bitlines, DZS, Power reduction
Citation:
Yen-Jen Chang, Feipei Lai, "Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories," IEEE Micro, vol. 25, no. 4, pp. 20-32, July-Aug. 2005, doi:10.1109/MM.2005.64
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