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July/August 2005 (vol. 25 no. 4)
pp. 5-6
IEEE Micro editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.
Index Terms:
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
Citation:
Pradip Bose, "Presilicon modeling: challenges in the late CMOS era," IEEE Micro, vol. 25, no. 4, pp. 5-6, July-Aug. 2005, doi:10.1109/MM.2005.74
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