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July/August 2005 (vol. 25 no. 4)
pp. 5-6
ASCII Text
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Pradip Bose, "Presilicon modeling: challenges in the late CMOS era," IEEE Micro, vol. 25, no. 4, pp. 5-6, July/August, 2005.
 
 
BibTex
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@article{ 10.1109/MM.2005.74,
author = {Pradip Bose},
title = {Presilicon modeling: challenges in the late CMOS era},
journal ={IEEE Micro},
volume = {25},
number = {4},
issn = {0272-1732},
year = {2005},
pages = {5-6},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.74},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Presilicon modeling: challenges in the late CMOS era
IS - 4
SN - 0272-1732
SP5
EP6
EPD - 5-6
A1 - Pradip Bose,
PY - 2005
KW - Integrated microarchitectures
KW - special purpose accelerators
KW - scalable on-chip interconnection network
KW - presilicon modeling
KW - CMOS
VL - 25
JA - IEEE Micro
ER -
 
IEEE Micro editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.
Index Terms:
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
Citation:
Pradip Bose, "Presilicon modeling: challenges in the late CMOS era," IEEE Micro, vol. 25, no. 4, pp. 5-6, July-Aug. 2005, doi:10.1109/MM.2005.74
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