• Utilization monitors. Built-in utilization monitors could adapt the computing resources in tune with input workload requirements. Such an architecture, supported by clock- and/or power-gating circuitry, would give designers a handle on minimizing average power consumption. This is good if the goal is to save on the battery power in portable computers or the electric bills that sustain a server farm. Limiting maximum power consumption and temperature (which is important in reducing the cost of the chip package and therefore the overall cost-performance ratio), would require additional controls. For example, throttling the clock or the instruction flow rates on detecting a power or temperature overrun is a commonly used mechanism.
• GALS design. The use of multiple voltage or clock domains permits a globally asynchronous locally synchronous design. The decoupling, asynchronous queues connecting the information flow from one domain to another serve as adjustable "springs" that correct for unpredictable speed variations in each domain.
• Reliability controls. Reliability monitoring, budgeting, and dynamic management can help keep lifetime failure rates within design specifications. Understanding the vulnerable hot spots in a chip and intelligently managing the distribution of tasks across multiple (possibly redundant) resources to keep temperatures and long-term failure probabilities within budget are the goals of this set of hardware controls.
• Enhanced error detection and recovery. Using pervasive error detection and correction circuitry, where feasible, prevents the storing of corrupt data in architected register or memory state, in the presence of soft errors. To support highly reliable computing, designs can even use lock-step duplicated (redundant) computation, backed by ECC-protected checkpointing and recovery mechanisms.