Issue No.02 - March/April (2005 vol.25)
Rajesh Kota , Newisys Inc.
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.28
Horus lets server vendors design up to 32-way Opteron systems. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent HyperTransport transaction.
Computer System Implementation Multiprocessor Systems
Rajesh Kota, "Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems", IEEE Micro, vol.25, no. 2, pp. 30-40, March/April 2005, doi:10.1109/MM.2005.28