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Niagara: A 32-Way Multithreaded Sparc Processor
March/April 2005 (vol. 25 no. 2)
pp. 21-29
| ASCII Text | x | ||
| Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, March/April, 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2005.35, author = {Poonacha Kongetira and Kathirgamar Aingaran and Kunle Olukotun}, title = {Niagara: A 32-Way Multithreaded Sparc Processor}, journal ={IEEE Micro}, volume = {25}, number = {2}, issn = {0272-1732}, year = {2005}, pages = {21-29}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.35}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Niagara: A 32-Way Multithreaded Sparc Processor IS - 2 SN - 0272-1732 SP21 EP29 EPD - 21-29 A1 - Poonacha Kongetira, A1 - Kathirgamar Aingaran, A1 - Kunle Olukotun, PY - 2005 KW - Microprocessors and microcomputers KW - Shared memory KW - Multithreaded processors VL - 25 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.35
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.
Index Terms:
Microprocessors and microcomputers, Shared memory, Multithreaded processors
Citation:
Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, March-April 2005, doi:10.1109/MM.2005.35
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