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Montecito: A Dual-Core, Dual-Thread Itanium Processor
March/April 2005 (vol. 25 no. 2)
pp. 10-20
| ASCII Text | x | ||
| Cameron McNairy, Rohit Bhatia, "Montecito: A Dual-Core, Dual-Thread Itanium Processor," IEEE Micro, vol. 25, no. 2, pp. 10-20, March/April, 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2005.34, author = {Cameron McNairy and Rohit Bhatia}, title = {Montecito: A Dual-Core, Dual-Thread Itanium Processor}, journal ={IEEE Micro}, volume = {25}, number = {2}, issn = {0272-1732}, year = {2005}, pages = {10-20}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.34}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Montecito: A Dual-Core, Dual-Thread Itanium Processor IS - 2 SN - 0272-1732 SP10 EP20 EPD - 10-20 A1 - Cameron McNairy, A1 - Rohit Bhatia, PY - 2005 KW - Multithreaded processors KW - Power Management KW - Reliability KW - Testing KW - and Fault-Tolerance KW - Cache memories VL - 25 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.34
Intel's Montecito is the first Itanium processor to feature duplicate, dual-thread cores and cache hierarchies on a single die. It features a landmark 1.72 billion transistors and server-focused technologies, and it requires only 100 watts of power.
Index Terms:
Multithreaded processors, Power Management, Reliability, Testing, and Fault-Tolerance, Cache memories
Citation:
Cameron McNairy, Rohit Bhatia, "Montecito: A Dual-Core, Dual-Thread Itanium Processor," IEEE Micro, vol. 25, no. 2, pp. 10-20, March-April 2005, doi:10.1109/MM.2005.34
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