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March/April 2005 (vol. 25 no. 2)
pp. 5
As we introduce this year?s Hot Chips theme issue, the frequency slowdown trend that is upon us as a result of the CMOS technology outlook has to be the single major point that stands out. It is not just the per-chip power dissipation envelope that is forcing this trend, although that factor alone is perhaps the major deterrent to frequency escalation at prior (historical) rates.
Citation:
Pradip Bose, "Variation-tolerant design," IEEE Micro, vol. 25, no. 2, pp. 5, March-April 2005, doi:10.1109/MM.2005.40
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