This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
January/February 2005 (vol. 25 no. 1)
pp. 30-40
Thomas H. Dunigan Jr., Oak Ridge National Laboratory
Jeffrey S. Vetter, Oak Ridge National Laboratory
James B. White III, Oak Ridge National Laboratory
Patrick H. Worley, Oak Ridge National Laboratory
The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. Our results show that this high bandwidth and low latency for remote memory accesses translate into improved application performance on important applications.
Citation:
Thomas H. Dunigan Jr., Jeffrey S. Vetter, James B. White III, Patrick H. Worley, "Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture," IEEE Micro, vol. 25, no. 1, pp. 30-40, Jan.-Feb. 2005, doi:10.1109/MM.2005.20
Usage of this product signifies your acceptance of the Terms of Use.