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Scalable Hardware Memory Disambiguation for High-ILP Processors
November/December 2004 (vol. 24 no. 6)
pp. 118-127
Simha Sethumadhavan, The University of Texas at Austin
Rajagopalan Desikan, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
Charles R. Moore, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state proportional to the instruction window size. A new class of solutions yields an order-of-magnitude reduction in the energy required to properly order loads and stores for windows of hundreds to thousands of in-flight instructions.
Citation:
Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler, "Scalable Hardware Memory Disambiguation for High-ILP Processors," IEEE Micro, vol. 24, no. 6, pp. 118-127, Nov.-Dec. 2004, doi:10.1109/MM.2004.87
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