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The Vector-Thread Architecture
November/December 2004 (vol. 24 no. 6)
pp. 84-90
Ronny Krashinsky, Massachusetts Institute of Technology
Christopher Batten, Massachusetts Institute of Technology
Mark Hampton, Massachusetts Institute of Technology
Steve Gerding, Massachusetts Institute of Technology
Brian Pharris, Massachusetts Institute of Technology
Jared Casper, Massachusetts Institute of Technology
Krste Asanovic, Massachusetts Institute of Technology
The vector-thread (VT) architecture supports a seamless intermingling of vector and multithreaded computation to flexibly and compactly encode application parallelism and locality. VT processors exploit this encoding to provide high performance with low power and small area.
Citation:
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic, "The Vector-Thread Architecture," IEEE Micro, vol. 24, no. 6, pp. 84-90, Nov.-Dec. 2004, doi:10.1109/MM.2004.90
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