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The Vector-Thread Architecture
November/December 2004 (vol. 24 no. 6)
pp. 84-90
ASCII Text
x 
 
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic, "The Vector-Thread Architecture," IEEE Micro, vol. 24, no. 6, pp. 84-90, November/December, 2004.
 
 
BibTex
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@article{ 10.1109/MM.2004.90,
author = {Ronny Krashinsky and Christopher Batten and Mark Hampton and Steve Gerding and Brian Pharris and Jared Casper and Krste Asanovic},
title = {The Vector-Thread Architecture},
journal ={IEEE Micro},
volume = {24},
number = {6},
issn = {0272-1732},
year = {2004},
pages = {84-90},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.90},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - The Vector-Thread Architecture
IS - 6
SN - 0272-1732
SP84
EP90
EPD - 84-90
A1 - Ronny Krashinsky,
A1 - Christopher Batten,
A1 - Mark Hampton,
A1 - Steve Gerding,
A1 - Brian Pharris,
A1 - Jared Casper,
A1 - Krste Asanovic,
PY - 2004
VL - 24
JA - IEEE Micro
ER -
 
Ronny Krashinsky, Massachusetts Institute of Technology
Christopher Batten, Massachusetts Institute of Technology
Mark Hampton, Massachusetts Institute of Technology
Steve Gerding, Massachusetts Institute of Technology
Brian Pharris, Massachusetts Institute of Technology
Jared Casper, Massachusetts Institute of Technology
Krste Asanovic, Massachusetts Institute of Technology
The vector-thread (VT) architecture supports a seamless intermingling of vector and multithreaded computation to flexibly and compactly encode application parallelism and locality. VT processors exploit this encoding to provide high performance with low power and small area.
Citation:
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic, "The Vector-Thread Architecture," IEEE Micro, vol. 24, no. 6, pp. 84-90, Nov.-Dec. 2004, doi:10.1109/MM.2004.90
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